Creating a Hardware Platform for the Platform-Based Design Flow - Creating a Hardware Platform for the Platform-Based Design Flow - 2026.1 English - UG1387

An extensible platform is the foundation of the platform-based design flow in the Vitis environment. The platform insulates application developers from the details of the low-level infrastructure. It lets them focus on developing a specific function in the processing system. Examples include software, AI Engine graph, or PL kernel logic.

Using the Vitis environment, a developer can add AI Engine and PL kernels to an extensible platform. The kernels added using the Vitis environment automatically have access to memories, interrupt controllers, resets, and clocking resources contained in the platform.

A Vitis extensible platform comprises both a hardware component and a software component. Vivado IP integrator designs the hardware components of a platform. The Vitis or PetaLinux tool chain creates the software components of a platform.

This section describes the flow used to create and configure hardware components of a platform using the IP integrator. For information on creating the software platform and packaging the entire platform, refer to Building Custom Platforms in the Embedded Design Development Using Vitis (UG1701).

The design created using the IP integrator must capture the foundational Versal adaptive SoC hardware IP blocks. These blocks include CIPS/PS Wizard, NoC, I/O controllers, and AI Engine array. The design must also expose logical interfaces. Later on, the Vitis v++ linker can connect kernels to these interfaces. Configure the processors, memory, and all external board interfaces using a combination of AMD IP, custom IP, and RTL.

The following figure shows an example of the block diagram for a hardware platform.

Following are the steps to build a hardware platform in IP integrator.

1. Instantiate the necessary IP to create the hardware portion of the platform.

   This can include configuring certain IP to meet the needs of the intended platform. These IP are the CIPS/PS Wizard, NoC, Processor System Reset Module, and Clocking Wizard IP. The input and output pins of these blocks are used by the hardware functions. The Vitis tools build the hardware functions at a later step.

2. Build a block design in the IP integrator. Declare and add platform (PFM) interfaces and properties on the IP blocks. Export the design as a hardware platform to the Vitis environment.

   These platform settings include clocking, interrupts, resets, memory, and processor AXI interfaces required for hardware functions within the Vitis environment. The IP integrator GUI provides a Platform Setup window to declare these interfaces along with their properties.

   Following are requirements for the PFM step:

   • There must be at least one enabled AXI port master interface within the platform.
   • A platform can have one or more clocks. There must be at least one enabled clock interface within the platform. If a hardware function uses a particular clock, then it uses the synchronized reset output for that clock.
   • The platform typically connects interrupts via the Concat block.
3. Export the hardware definition (XSA) to the Vitis environment after generating the design.

   This exports the necessary XML files for the Vitis tools to interpret the IP used in the design. It also exports the memory mapping from the processor perspective.

You must package the exported XSA with the software components after creating the hardware platform. This creates the entire Vitis platform for use with the v++ compiler/linker.

For more information on IP integrator, refer to the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994).