Creating Synthesis Constraints - Creating Synthesis Constraints - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)
Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English

Synthesis takes the RTL description of the design and transforms it into an optimized technology mapped netlist by using timing-driven algorithms. The quality of the results is affected by the quality of the RTL code and the constraints provided. At this point of the compilation flow, the net delay modeling is approximate and does not reflect placement constraints or complex effects such as congestion. The main objective is to obtain a netlist which meets timing, or fails by a small amount, with realistic and simple constraints.

The synthesis engine accepts all XDC commands, but only some have a real effect:

  • Timing constraints related to setup/recovery analysis influence the QoR:
    • create_clock / create_generated_clock
    • set_input_delay / set_output_delay
    • set_clock_groups / set_false_path / set_max_delay / set_multicycle_path
  • The synthesis process ignores ignores timing constraints related to hold and removal analysis:
    • set_min_delay / set_false_path -hold / set_multicycle_path -hold
  • RTL attributes forces decisions made by the mapping and optimization algorithms. Following are a few examples:
    • DONT_TOUCH / KEEP / KEEP_HIERARCHY / MARK_DEBUG
    • MAX_FANOUT
    • RAM_STYLE / ROM_STYLE / USE_DSP / SHREG_EXTRACT
    • FULL_CASE / PARALLEL_CASE (Verilog RTL only)
    Note: You can also set the same attribute as a property from an XDC file. Using XDC-based constraints is convenient for influencing the synthesis results only in some cases without changing the RTL.
  • The system ignores physical constraints such as LOC, BEL, and Pblocks.

Synthesis constraints must use names from the elaborated netlist, preferably ports and sequential cells. During elaboration, some RTL signals can disappear and it is not possible to attach XDC constraints to them. In addition, the system merges nets or logical cells into various technology primitives, such as LUTs or DSP blocks, due to various optimizations after elaboration. To know the elaborated names of your design objects, click Open Elaborated Design in the Flow Navigator and browse to the hierarchy of interest.

The system absorbs some registers into RAM blocks. It can also eliminate some levels of the hierarchy to allow cross-boundary optimizations.

Use a DONT_TOUCH, KEEP, KEEP_HIERARCHY, or MARK_DEBUG constraint to preserve any elaborated netlist object or level of hierarchy. This can risk degrading timing or area QoR.

Finally, some constraints can conflict and cannot be respected by synthesis. For example, a MAX_FANOUT attribute is set on a net that crosses multiple levels of hierarchy. Some hierarchies are preserved with DONT_TOUCH. In that case, those conditions limit or fully prevent fanout optimization.

Important: Unlike during implementation, synthesis can optimize away RTL netlist objects used to define timing constraints to allow better area QoR. This is usually not a problem as long as you update and validate the constraints for implementation. But if needed, you can preserve any object by using the KEEP constraint so that the constraints apply during both synthesis and implementation.

After synthesis is complete, AMD recommends that you review the timing and utilization reports. This review validates that the netlist quality meets the application requirements. Use the netlist for implementation.