The implementation constraints must accurately reflect the requirements of the final application. The board design dictates physical constraints such as I/O location and I/O standard. This includes board trace delays and design internal requirements derived from the overall system requirements. Before you proceed to implementation, AMD highly recommends that you validate the correctness and accuracy of all your constraints. An improper constraint likely contributes to degradation of the implementation QoR and can lower the confidence level in the timing signoff quality.
You can use the same constraints during synthesis and implementation in many cases. The design objects can disappear or have their name changed during synthesis. You must verify that all synthesis constraints still apply properly with the implementation netlist. If this is not the case, you must create an additional XDC file containing the constraints that are valid for implementation only.