Creating Generated Clocks - Creating Generated Clocks - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English

A generated clock is a clock derived from another existing clock called the master clock. It usually describes a waveform transformation performed on the master clock by a logic block. Define the master clock first because the generated clock definition depends on the master clock characteristics. Use the create_generated_clock command to explicitly define a generated clock.