Coding an incomplete conditional statement into a synchronous block creates clock enables. The clock enable retains the last value. When prior conditions are not met, it performs this action. When this is the required functionality, it is valid to code in this manner.
However, the output is a don't care.
The system does not meet prior conditional values, causing this to happen. AMD recommends closing off the conditional by using an
else clause. Assign the signal to a one or a zero as
a defined constant.
In most implementations, this does not result in added logic, and avoids the need for a clock enable. In the case of a large bus, inferring a clock enable can help reduce power by holding the value. This is the exception to the rule.
The basic premise holds that using a clock enable can make inferring small numbers of registers detrimental. This is because it increases control set count. However, in larger groups, it can become more beneficial and is recommended.