When working on a multi-team project, it is convenient to create individual constraint files for each major block of the top-level design. Developers usually create and validate each of these blocks separately. They then integrate the blocks into one or many top-level designs.
Develop block-level constraints independently from the top-level constraints. Ensure they are as generic as possible to allow use in various contexts. In addition, these constraints must not affect any logic that is beyond the block boundaries.
When implementing a sub-block, include the full clocking network in timing analysis. This ensures accurate skew and clock domain crossing analysis. This can require an HDL wrapper containing the clocking components and an additional constraint file to replicate top level clocking constraints. Use it only for the timing validation of the submodule.
Refer to this link in the Vivado Design Suite User Guide: Using Constraints (UG903) for more information on constraints scoping. This guide also includes rules, guidelines, and mechanisms for loading the block-level constraints into the top-level design.