Corner Banks - Corner Banks - 2026.1 English - UG1387

The XPIO/X5IO banking resources sit adjacent to certain resources, such as the processing system (PS) or high-speed transceiver columns. In this case, the XPIO/X5IO banks have reduced functionality. Restricted XPIO/X5IO banks typically occupy the device corners and are called corner banks. Corner bank locations vary by device. The Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013) explicitly calls them out with a DDRMC designation.

Following are considerations when working with corner banks:

• Although clocking pins (GC) in corner banks have full access to clocking resources, non-clocking pins are restricted to the DDR memory controller functionality. The DDR memory controller can restrict a partial bank on nibble boundaries. Typically, it defines the bank along bank boundaries.
• In pin planning a Versal adaptive SoC design, use corner banks for DDR memory controller interfaces only. When you use the Advanced I/O Planner for Advanced I/O Wizard/X5IO Wizard designs, it blocks the corner banks from use.
• When using GC inputs to drive XPIO/X5IO corner banks, you cannot place clock buffers BUFGCTRL and BUFGCE_DIV after MMCM. The sites are reserved. The corner bank affected is below the PS (bottom left corner) and does not have full access to programmable logic resources. There is no restriction for the corner bank below the GTs at the bottom right corner.
• Use an MMCM in the restricted corner bank when needed. The MMCM output clock must go through a BUFGCE. This is necessary to reach any other loads, including BUFGCTRL or BUFGCE_DIV.