The code already contains clock gating constructs. It can be intended for a different technology that requires such coding styles. AMD recommends using a synthesis tool. The tool can remap gates placed within the clock path to clock enables in the data path. This approach improves mapping to the clocking resources and simplifies the timing analysis of the circuit for data entering and exiting the gated domain.
For example, use the -gated_clock_conversion
auto option with Vivado synthesis to
attempt automatic conversion to register clock enable logic. For the complex gated clock
structures, use the GATED_CLOCK attribute in the RTL code to guide Vivado synthesis.