After the device completes configuration, a sequence of events occurs in which the device completes the configuration state and enters into general operation. In most configuration sequences, one of the last steps is the deassertion of the Global Set Reset (GSR). This is followed by the deassertion of the Global Enable (GWE) signal. When this happens, the design is in a known initial state and is then released for operation.
Synchronize the release point to the given clock domain. The clock must operate faster than the GWE can safely be released. If these conditions are not met, portions of the design can go into an unknown state. For some designs, this does not matter. In other designs, this can cause the design to become unstable or to incorrectly process the initial data set.
If the design must start up in a known state, take action to control the start-up synchronization process. AMD recommends using any of the following methods:
- Use clock enables, local reset (synchronized), or both on critical parts of the design. Such parts include a state machine. This controls and defines the start-up of those portions of the design.
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Use instantiated clock buffer components with clock enable capability.
Delay the reset release by as many cycles as needed before enabling the design clock. The following example shows how to delay the first design clock edge after you release the reset. Set ASYNC_REG=TRUE on the synchronizer registers. This places all registers in a single SLICE and they do not need a global clock resource. To prevent clock buffer insertion on the synchronizer clock, use the CLOCK_BUFFER_TYPE=NONE property on the input clock port.
Figure 1. Reset Synchronization and Delay for Safe Clock Startup Example
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When using an MMCM, select the Safe Clock Startup option from the Clocking Wizard. This ensures design clocks are enabled only after they are stable and reliable.
The following example shows the synchronization stages of an MMCM LOCKED signal connected to the CE pin of the BUFGCE, which drives the user logic. The logic controlling the BUFGCE/CE pin connects a second BUFGCE in parallel to the high fanout BUFGCE (user clock). This topology helps timing closure on the BUFGCE/CE by minimizing the clock skew between the synchronizer and the BUFGCE pin.
Figure 2. MMCM Safe Clock Startup Example
Tip: The MMCM compensation mode groups all clocks from CLKOUT0 with the feedback clock when it uses BUF_IN. These clocks use the same CLOCK_ROOT. If this introduces timing violations on BUFGCE/CE, create a CLOCK_DELAY_GROUP constraint between the high fanout clock and the feedback clock only.Optionally, you can also set a CLOCK_LOW_FANOUT constraint on the low fanout clock net. This results in load placement in the same clock region as the BUFG and MMCM.