You can force control set mapping by applying the DIRECT_RESET/DIRECT_ENABLE/EXTRACT_RESET/EXTRACT_ENABLE attributes as needed. This handles the mapping of control sets for a given structure.
The design includes a synchronous reset/enable.
Synthesis creates a logic cone mapped through the CE/R/S pins. This occurs when the load
is equal to or above the threshold set by the -control_set_opt_threshold synthesis switch. Synthesis creates a logic
cone that maps through the D pin if the load is below the threshold. The default
threshold for Versal adaptive SoC is 2.