You must specify the location and I/O standard for each port of the design. You must also specify Input and output delay constraints. These constraints describe the timing of external paths to and from the device interface.
The board usually generates a clock, which enters the device, to define these delays relative to it. In some cases, define the delays in relation to a virtual clock. This is necessary when the I/O path relates to a clock with a waveform different from the board clock.
Important: Constrain
I/O delays only for interfaces that use I/O logic, such as IDDR/ODDR/IOB registers or fabric.
For high-speed I/O interfaces in Versal adaptive SoC,
AMD provides the Advanced IO Wizard and Advanced I/O
Planner. The Advanced IO Wizard configures the XPHY and can be used to estimate the I/O timing
for the interface. For more information about the Advanced IO Wizard, refer to the
Advanced IO Wizard LogiCORE IP Product Guide
(PG320).