Constraining Exclusive Clock Groups - Constraining Exclusive Clock Groups - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English

You can use the regular timing or clock network reports to review the clock paths. These reports help identify the situations where two clocks propagate on a same clock tree. A timing path uses the clocks simultaneously. The same clock tree connects the startpoint and endpoint clock pins.

This analysis can be a time consuming task. Instead, you can review the multiple_clock section of the Check Timing report. This section returns a list of clock pins and their associated timing clocks.

Based on the clock tree topology, you must apply different constraints as described in the following sections.