Common Mistakes - Common Mistakes - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English

Following are common mistakes that you must avoid:

  • Relaxing setup without adjusting hold back to same launch and capture edges. This is in the case of a multicycle path not functionally active at every clock cycle.

    The hold requirement can become High (at least one clock period in most cases) and impossible to meet.

  • Setting a multicycle path exception between incorrect points in the design.

    This occurs when you assume that there is only one path from a startpoint cell to an endpoint cell. In some cases, this is not true. The endpoint cell can have multiple data input pins, including clock enable and reset pins, which are active on at least two consecutive clock edges.

    For this reason, AMD recommends specifying the endpoint pin instead of the cell (or clock). For example, the endpoint cell REGB has three input pins: C, EN, and D.

    Constrain only the REGB/D pin with the multicycle path exception. Do not constrain the EN pin because it can change at every clock cycle. The constraints consider all valid endpoint pins, including the EN (clock enable) pin, when attached to a cell instead of a pin.

    To be safe, AMD recommends that you always use the following syntax:
    set_multicycle_path -from [get_pins REGA/C] \
    -to [get_pins REGB/D] -setup 3
    set_multicycle_path -from [get_pins REGA/C] \
    -to [get_pins REGB/D] -hold 2