Coding Recommendations for Creating and Packaging RTL Kernels for the Platform-Based Design Flow - Coding Recommendations for Creating and Packaging RTL Kernels for the Platform-Based Design Flow - 2026.1 English - UG1387

The platform-based design flow for Versal adaptive SoC makes it easy to use existing RTL code or Vivado IP as Vitis kernels. Vitis kernels are well-formalized design blocks. The Vitis v++ linker can automatically integrate them into extensible platforms in a correct-by-construction manner.