Versal devices allow clock tile splitting among multiple RPs. Specify the range for the clock sources, such as MMCM and BUFG, to the Pblock. The DFX flow automatically uses the required clocking tiles for routing.
The following figure shows the RCLK row and the vertical NoC (VNoC) column sharing multiple RPs. In the RCLK row, two RPs share the same clock region; one above the RCLK row and one below. Multiple RPs also share the VNoC tiles.
Recommended:
AMD recommends keeping a clock region gap between the RPs if your
design includes more than two RPs. This prevents RP internal clocks from using clock
routing in the same VNoC tile. If more than two RPs attempt to use clock routing in a
single VNoC column, an unroutable situation can occur.
Figure 1. RCLK Row and Vertical NoC Column Sharing Multiple RPs
