A clock phase shift corresponds to a delayed clock waveform with respect to a reference clock due to special hardware in the clock path. In AMD devices, the MMCM, XPLL, or DPLL primitives usually introduce clock phase shift when their output clock CLKOUT*_PHASE property is non-zero.
You can model the clock phase shift in two ways using analog deskew. Model it as a change in the clock waveform by setting PHASESHIFT_MODE=WAVEFORM. You can model it as a delay through the MMCM or XPLL (PHASESHIFT_MODE=LATENCY). In Versal devices, the default modeling for the clock phase shift is as a delay through the clocking primitive.
Refer to this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906) for more information about clock phase shift modeling. This guide also covers the PHASESHIFT_MODE property.
Following are additional notes:
- The DPLL or MMCM/XPLL supports only the PHASESHIFT_MODE=LATENCY configuration when configured with digital deskew.
- If you configure an MMCM/XPLL/DPLL with digital deskew and set
PHASESHIFT_MODE=WAVEFORM, Report Methodology reports the following
warning:
TIMING-54: The clock modifying block <MMCM/XPLL/DPLL> is configured for digital deskew and has PHASESHIFT_MODE=WAVEFORM. This combination is unsupported, and timing analysis will proceed by treating it as if PHASESHIFT_MODE=LATENCY. Change the specified cell configuration to PHASESHIFT_MODE=LATENCY and ensure that no timing constraints are written against the expectation of PHASESHIFT_MODE=WAVEFORM.