Clock Latency at the Source - Clock Latency at the Source - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English

It is possible to model the latency of a clock at its source by using the set_clock_latency command with the -source option. This is useful in two cases:

  • To specify the clock delay propagation outside the device independently from the input and output delay constraints.
  • To model the internal propagation latency of a clock used by a block during out-of-context compilation. In such a compilation flow, the description of the complete clock tree is absent. Therefore, you cannot automatically compute the variation between min and max operating conditions outside the block. You must manually model this variation.
Note: Only advanced users must use this constraint, as providing valid latency values is usually difficult.