The report_clock_utilization command provides
details on clock primitive utilization. Observe the architecture clocking rules to avoid
downstream placement issues. Invalid placement constraints or high fanout for regional
clock buffers can cause issues in the placer. For designs with high clock buffer
utilization, it can be necessary to lock the clock generators and some regional clock
buffers to aid placement.
For interfaces requiring tight timing relationship, it is often best to lock specific resources to signals needing tight timing relationship, such as source synchronous interfaces. Typically, as a starting point for your design, lock only the I/Os. Do not follow this approach if there are specific reasons not to, as cited above.