You can use the output pin of certain hardware primitives as the primary clock root. The output pin shown in the following figure is an example. It does not have a timing arc from an input pin of the same primitive.
Figure 1. Clock Path Broken Due to a Missing Timing Arc
Important: You must not define a primary
clock in the transitive fanout of another primary clock because this situation does not
correspond to any hardware reality. It also prevents proper timing analysis by
preventing the complete clock insertion delay calculation. Revisit and correct the
constraints whenever this situation occurs.
The following figure shows an example where the transitive fanout of the clock
clk0 defines the clock clk1. The clock clk1 overrides clk0 starting at the output of BUFG1, where it is defined.
Therefore, the timing analysis between REGA and REGB is not accurate because of the
invalid skew computation between clk0 and clk1.
Figure 2. create_clock in the Fanout of Another Clock is Not
Recommended
