The maximum clock extent that affects FMAX is the sum of the fabric clock regions traversed by the clock routing and distribution network. The horizontal route through the XPIO clock regions does not contribute to a decrease in FMAX. Assigning the clock root in the center-most vertical NoC column for a given clock network improves the FMAX.
In the example below, a BUFGCE in clock region X12Y0 drives clock loads in clock columns X2, X3, X4, X5, X6, X7, X8, and X9. The clock root X7Y4 on the left lowers FMAX. This occurs because two additional fabric clock regions are traversed horizontally. The traversal is for the maximum clock extent. The left picture shows the more optimal clock root X5Y4 for comparison.
Assign the clock root in the most central vertical NoC column using the USER_CLOCK_ROOT property:
set_property USER_CLOCK_ROOT X5Y4 [get_nets -of [get_pins BUFGCE_inst/O]]