You can expand the path schematics to the first level of sequential cells for each port. Then, trace the clock pins of those cells back to the clock source(s). High fanout nets can make this approach impractical for connected ports.
You can expand the path schematics to the first level of sequential cells for each port. Then, trace the clock pins of those cells back to the clock source(s). High fanout nets can make this approach impractical for connected ports.