Browse the Board Schematics - Browse the Board Schematics - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English

The board connects a group of I/O ports to another device interface. You can use the board clock as the reference clock. The board clock connects to both the AMD device and the external device interface. Use it for the input or output delay constraints.

Check the external device data sheet to confirm that the board clock transforms internally to time the I/O ports. This transformation controls the timing of the related group of ports. It ensures that the design generates the same clock inside the AMD device.