After the first implementation, the system locks the boundary clock net tracks. The partition pin locations (PPLOCs) on the boundary clock nets reach all clock regions covered by the reconfigurable partition (RP) Pblock.
You can place the clock root of the boundary clock net anywhere in the device. The boundary clock net can drive both static and RP loads. AMD recommends using the USER_CLOCK_ROOT constraint on the boundary clock net to manually constrain the CLOCK_ROOT location due to the following:
- If the boundary clock loads are mainly in the static region, the system can place the clock root there.
- If the first implementation uses training logic in the RP Pblock, boundary clock nets can be locked down after the first implementation. In that case, the clock root location can be off-center.
- The RP Pblock distributes the boundary clock net to all covered clock
regions. This distribution causes the clock insertion delay for the boundary clock
to be relatively high. The delay is high compared with the internal RM clock
nets.Note: Versal devices with SSI technology have stricter requirements for the clock root. The clock root is generally placed at the top of a super logic regions (SLRs). This placement is for clock nets spanning multiple SLRs. It sits in the middle of the device. This placement helps to balance the clock tree.
Therefore, AMD recommends that you avoid using boundary clocks for timing critical paths in your design that require low clock insertion delays.