Local clocks are clock nets routed with regular fabric resources instead of dedicated global clocking resources. In most cases, the Vivado synthesis and Vivado logic optimization tools insert clock buffers where the architecture mandates them. Also, the tools insert them for clock nets with more than 30 clock loads. Local clocks typically occur when:
- Fabric logic implements a counter that divides a global clock
- Clock gating conversion is not able to remove all LUTs from the clock path
In general, avoid using local clocks. Local clocks introduce several challenges to the implementation tools:
- Unpredictable clock skew, leading to difficult timing closure
- Low to medium fanout nets increase, and the router processes them
with special care, leading to potential routability problems Tip: If local clocks introduce timing QoR problems, try floorplanning the clock driver and loads to a small area using a Pblock. Use
report_clock_utilizationto identify the location of the local clocks, review the clock placement, and decide on how to reduce their number or impact.
The BUFG_FABRIC cell in Versal devices routes a net from regular fabric resources to the
dedicated global clocking resources. BUFG_FABRIC sites exist throughout the device in
NoC columns. They route high fanout nets on global clocking resources, such as resets
and clock enables.
CAUTION:
Do not use the BUFG_FABRIC cell for clock nets to access the global
clocking resources. Use BUFG_FABRIC if your local clock requires the global clock
network and you cannot directly access the global clocking resources. It can route
the local clock onto the global clock network. The resulting clock has suboptimal
timing characteristics when compared to a clock that has direct access to the global
clocking resources.