A clock route through the GT column that crosses the SLR boundary results in a lower supported FMAX. The analysis compares this to the same clock route and extent through the vertical NoC column. You can improve performance for clock networks that extend across the SLR boundary. Choose a clock root in one of the vertical NoC columns. Avoid choosing the GT column.
In the example below, a BUFG_GT in clock region X9Y4 drives clock loads in clock columns X6, X7, X8, and X9. The clock root X9Y4 on the left results in a lower FMAX because the vertical distribution crosses the SLR boundary in the GT clocking column. The clock root X7Y4 on the right improves FMAX because it crosses the SLR boundary in the vertical NoC column. Use the USER_CLOCK_ROOT property to assign the clock root in the vertical NoC column:
set_property USER_CLOCK_ROOT X7Y4 [get_nets -of [get_pins BUFG_GT_inst/O]]