The Vivado timing engine automatically derives most generated clocks. It recognizes the clock modifying blocks (CMB) and the transformations they perform on the master clocks.
In the AMD Versal™ device family, following are the CMBs:
- MMCM*/XPLL*/DPLL*
- BUFG_GT/BUFGCE_DIV
- MBUFG_PS/MBUFG_GT/MBUFGCE/MBUFGCE_DIV/MBUFGCTRL
- GTYE5_QUAD/GTYP_QUAD/GTME5_QUAD
- IBUFDS_GTE5/IBUFDS_GTME5
- XPHY
Timing clocks propagate through any other combinatorial cell located on the clock tree. You do not need to redefine them at their output unless the cell transforms the waveform. You must rely on the auto-derivation mechanism as much as possible. It provides the safest way to define the generated clocks. These clocks correspond to the actual hardware behavior.
The Vivado Design Suite timing engine can
choose an inappropriate auto-derived clock name. You can force your own clock name. Use
the create_generated_clock command without specifying
the waveform transformation. Place this constraint immediately after the constraint that
defines the master clock in the constraint file.
fftClk:create_generated_clock -name fftClk [get_pins mmcm_i/CLKOUT0]Attach the constraint to the source pin of the clock to avoid any ambiguity. For more information, refer to the Vivado Design Suite User Guide: Using Constraints (UG903).