Where possible, add I/O components near the top level for design readability. When you infer a component, you provide a description of the function you want to accomplish. The synthesis tool then interprets the HDL code to determine which hardware components to use to perform the function. The system can infer components such as simple single-ended I/O (IBUF, OBUF, OBUFT, and IOBUF) and single data rate registers in the I/O.
Use the tool to infer IOBUF or OBUFT components. Ensure the enable logic and the input/output logic are all in the same hierarchy. If the logic is in different hierarchies and there are KEEP_HIERARCHY or DONT_TOUCH attributes between the hierarchies, the tool cannot infer these buffers.
I/O components need to be instantiated near the top level. These components include differential I/O like IBUFDS and OBUFDS. Instantiate double data-rate registers, such as IDDR and ODDR, near the top level.
When you instantiate a component, you add an instance of that component to your HDL file. You fully control how you use the component through instantiation. You know exactly how to use the logic.