The Alveo™ U50/U50LV accelerator card supports two AMD UltraScale+™™ FPGA configuration modes:
- Quad SPI flash memory
- JTAG (through USB maintenance port)
The FPGA bank 0 mode pins are hardwired to master SPI mode M[2:0] =
001 with pull-up/down resistors.
At power up, the FPGA is configured by the Quad SPI NOR flash device
using the primary serial configuration mode. Refer to the XDC for recommended
configuration parameters specified via the various BITSTREAM.CONFIG constraints.
If the JTAG cable is plugged in, QSPI configuration might not occur. JTAG mode is always available independent of the mode pin settings.
For complete details on configuring the FPGA, see the UltraScale Architecture Configuration User Guide (UG570).
| Configuration Mode | M[2:0] | Bus Width | CCLK Direction |
|---|---|---|---|
| Master SPI | 001 | x1, x2, x4 | FPGA output |
| JTAG | Not applicable – JTAG overrides | x1 | Not applicable |