The following table lists various miscellaneous I/O signals for the Alveo U50/U50LV card. See the XDC file for additional signals and details.
Important: The J18 pin must be connected appropriately or tied to logic 0. If J18 is pulled
up, floated, or tied to 1, the U50/U50LV card might
become unrecoverable after programming. See HBM Memory for more information.
| Signal Name | Direction | Pin | I/O | Description |
|---|---|---|---|---|
| FPGA_RXD_MSP | Input | BB26 | IO_L13N_T2L_N1_GC_QBC_A07_D23_65 | Satellite controller CMS UART receive (115200, no parity, 8 bits, 1 stop bit). |
| FPGA_TXD_MSP | Output | BB25 | IO_L13P_T2L_N0_GC_QBC_A06_D22_65 | Satellite controller CMS UART transmit (115200, no parity, 8 bits, 1 stop bit). |
| PEX_PWRBRKN | Input | BD28 | IO_T3U_N12_PERSTN0_65 | Active-Low input from PCIe connector signaling PCIe card to shut down card power in server failing condition. |
| PCIE_PERST | Input | AW27 | IO_T3U_N12_PERSTN0_65 | Active-Low input from PCIe connector to FPGA to detect presence. |
| HBM_CATTRIP | Output | J18 | IO_L6N_T0U_N11_AD6N_68 | Active-High indicator to satellite controller to indicate the HBM has exceeded its maximum allowable temperature. This signal is not a dedicated FPGA output and is a derived signal in RTL. Making this signal active shuts off the FPGA power rails. |
| SYSCLK3_P | Input | BB18 | IO_L11P_T1U_N8_GC_64 | General purpose / HBM LVDS 100 MHz clock input from the SI53306 output port 3. Original 100 MHz signal is generated from output port 3 SI5394. |
| SYSCLK3_N | Input | BC18 | IO_L11N_T1U_N9_GC_64 | General purpose / HBM LVDS 100 MHz clock input from the SI53306 output port 3. Original 100 MHz signal is generated from output port 3 SI5394. |
| SYSCLK2_P | Input | G17 | IO_L11P_T1U_N8_GC_68 | General purpose LVDS 100 MHz clock input from the SI53306 output port 2. Original 100 MHz signal is generated from output port 3 SI5394. |
| SYSCLK2_N | Input | G16 | IO_L11N_T1U_N9_GC_68 | General purpose LVDS 100 MHz clock input from the SI53306 output port 2. Original 100 MHz signal is generated from output port 3 SI5394. |
| FPGA_UART0_RXD | Input | BF26 | IO_L15N_T2L_N5_AD11N_A03_D165 | Input from DBM-01 UART to FPGA |
| FPGA_UART0_TXD | Output | BE26 | IO_L15P_T2L_N4_AD11P_A02_D1_65 | Output from FPGA to DBM-01 UART |
| FPGA_UART1_RXD | Input | B15 | IO_L24P_T3U_N10_68 | Input from DBM-01 UART to FPGA |
| FPGA_UART1_TXD | Output | A17 | IO_L23N_T3U_N9_68 | Output from FPGA to DBM-01 UART |
| FPGA_UART2_RXD | Input | A18 | IO_L23P_T3U_N8_68 | Input from DBM-01 UART to FPGA |
| FPGA_UART2_TXD | Output | A19 | IO_L22N_T3U_N7_DBC_AD0N_68 | Output from FPGA to DBM-01 UART |
| SI_RSTB | Input | F20 | IO_L10N_T1U_N7_QBC_AD4N_68 | Active-Low reset output from FPGA to Si5394B input |
| SI_INTRB | Input | H18 | IO_L9P_T1L_N4_AD12P_68 | Active-Low interrupt output from Si5394B to FPGA input |
| SI_PLL_LOCKB | Input | G19 | IO_L8N_T1L_N3_AD5N_68 | Active-Low PLL Loss of Lock output from Si5394B to FPGA input |
| SI_IN_LOSB | Input | H19 | IO_L8P_T1L_N2_AD5P_68 | Active-Low PLL Loss of Signal output from Si5394B to FPGA input |
| I2C_SI5394_SCLK | Output | L19 | IO_L5P_T0U_N8_AD14P_68 | Master I2C clock connection from FPGA to Si5394B |
| I2C_SI5394_SDA | Bidirectional | J16 | IO_L4N_T0U_N7_DBC_AD7N_68 | Master I2C data connection from FPGA to Si5394B |
| ETH_RECOVERED_CLK_N | Input | F18 | IO_L12N_T1U_N11_GC_68 | 100 MHz LVDS clock from FPGA to Si5394B clock input ports IN0 for IEEE-1588 PTP |
| ETH_RECOVERED_CLK_P | Input | F19 | IO_L12P_T1U_N10_GC_68 | 100 MHz LVDS clock from FPGA to Si5394B clock input ports IN0 for IEEE-1588 PTP |
| QSFP28_0_ACTIVITY_LED | Output | E18 | IO_L14P_T2L_N2_GC_68 | Active-High signal from FPGA to illuminate QSFP green Activity LED |
| QSFP28_0_STATUS_LEDG | Output | E16 | IO_L13N_T2L_N1_GC_QBC_68 | Active-High signal from FPGA to illuminate QSFP green Status LED |
| QSFP28_0_STATUS_LEDY | Output | F17 | IO_L13P_T2L_N0_GC_QBC_68 | Active-High signal from FPGA to illuminate QSFP yellow Status LED |