MCS File Generation and Alveo Card Programming

This section outlines the steps to generate and program the MCS file.

Note: When creating a design for this card, it is necessary to drive the CATTRIP pin listed in the following table. This pin is monitored by the card's satellite controller (SC) and represents the HBM_CATTRIP (HBM catastrophic temperature failure). When instantiating the HBM IP in your design, the two HBM IP signals, DRAM_0_STAT_CATTRIP and DRAM_1_STAT_CATTRIP, must be ORed together and connected to this pin for proper card operation. If the pin is undefined it will be pulled High by the card causing the SC to infer a CATTRIP failure and shut power down to the card.

If you do not use the HBM IP in your design, you must drive the pin Low to avoid the SC shutting down the card. If the pin is undefined and the QSPI is programmed with the MCS file, there is a potential chance that the card will continuously power down and reset after the bitstream is loaded. This can result in the card being unusable.

MCS File Generation

The MCS file represents the PROM image which is loaded onto the Alveo accelerator card at power on. It is generated using the write_cfgmem tool. This section outlines the steps to generate and program the MCS file.

Prior to generating the MCS file, ensure your project XDC file sets the following properties.

CONFIG_VOLTAGE
BITSTREAM.CONFIG.CONFIGFALLBACK
BITSTREAM.GENERAL.COMPRESS
CONFIG_MODE
BITSTREAM.CONFIG.SPI_BUSWIDTH
BITSTREAM.CONFIG.CONFIGRATE
BITSTREAM.CONFIG.EXTMASTERCCLK_EN
BITSTREAM.CONFIG.SPI_FALL_EDGE
BITSTREAM.CONFIG.UNUSEDPIN
BITSTREAM.CONFIG.SPI_32BIT_ADDR

Use the following command with the parameters outlined in Table 1 to generate the MCS file.

write_cfgmem -force -format mcs -interface <interface_type> -size <size> -loadbit "up <user_config_region_offset> <input_file.bit>" -file "<output_file.mcs>"

Table 1. write_cfgmem Parameter Settings
write_cfgmem Parameter	Setting
interface_type	`spix4`
size	128
user_config_region_offset¹	`0x01002000`
input_file.bit	Filename of the input .bit file
output_file.mcs	MCS output filename
Address `0x00000000` through `0x01001FFF` is a write protected region which holds the card's golden recovery image and cannot be written to. The `user_config_region_offset` setting cannot be within this range.

For additional details on write_cfgmem, see the UltraScale Architecture Configuration User Guide (UG570).

Program the Alveo Data Center accelerator card

After the MCS file has been generated, use the following steps to flash the FPGA on the Alveo Data Center accelerator card using the Vivado hardware manager. Detailed steps for programming the FPGA are outlined in the chapter Programming the FPGA Device in the Vivado Design Suite User Guide: Programming and Debugging (UG908).

Connect to the Alveo U50/U50LV data center accelerator card using the Vivado hardware manager through the maintenance connector. Details on connecting to the Alveo card through the maintenance connector are provided in the Alveo Programming Cable User Guide (UG1377).
Select Add Configuration Device and select the mt25qu01g-spi-x1_x2_x4 part.
Select OK when prompted "Do you want to program the configuration memory device now?" or right-click the target to select Program the Configuration Memory Device.
1. Select the MCS file target.
2. Select Configuration File Only.
3. Click OK.
After programming has completed, disconnect the card in the hardware manager, and disconnect the JTAG programming cable from the Alveo accelerator card.
Perform a cold reboot on the host machine to complete the card update.

Important: When switching between an Alveo data center accelerator card target platform and a custom design, revert the card to the factory image before loading an alternate image into the PROM. See Answer Record 71757 for more information.