HBM Memory

This device contains two 4 GB high-bandwidth memory (HBM) stacks for a total of 8 GB HBM memory. There are 32 AXI interfaces along with an internal switch that provides access to the 8 GB memory space. For detailed information, refer to the AXI High Bandwidth Controller LogiCORE IP Product Guide (PG276). The extensive connections between the device and HBM stacks help with floorplanning and timing closure.

Note: When creating a design for this card, it is necessary to drive the CATTRIP pin listed in the following table. This pin is monitored by the card's satellite controller (SC) and represents the HBM_CATTRIP (HBM catastrophic temperature failure). When instantiating the HBM IP in your design, the two HBM IP signals, DRAM_0_STAT_CATTRIP and DRAM_1_STAT_CATTRIP, must be ORed together and connected to this pin for proper card operation. If the pin is undefined it will be pulled High by the card causing the SC to infer a CATTRIP failure and shut power down to the card.

If you do not use the HBM IP in your design, you must drive the pin Low to avoid the SC shutting down the card. If the pin is undefined and the QSPI is programmed with the MCS file, there is a potential chance that the card will continuously power down and reset after the bitstream is loaded. This can result in the card becoming unusable.

Table 1. HBM CATTRIP Pin Connection
Signal Name	Direction	Bank	I/O Reference	Pin	Description
HBM_CATTRIP_LS	Output	68	IO_L6N_T0U_N11_AD6N_68_J18	J18	Catastrophic temperature indicator to the SC (Active-High)