Design Flows

The preferred optimal design flow for targeting the Alveo data center accelerator card uses the AMD Vitis™ unified software platform. However, traditional design flows, such as RTL or IP integrator are also supported using the AMD Vivado™ Design Suite. The following figure shows a summary of the design flows.

Figure 1. Alveo Data Center Accelerator Card Design Flows

Documents related to the different design flows are listed in the following table. Additional details on the Vivado design flow are given in Vivado Design Flow.

For the Vitis design flow details, see Vitis Unified Software Platform Documentation (UG1416).

Table 1. Documentation to Get Started with Alveo Data Center Accelerator Card Design Flows
	RTL Flow	IP Integrator Flow	Vitis
Flow documentation	UG949¹	UG994²	UG1416³
Vivado tools support	Board support XDC	Vivado Board File	N/A
Programming the FPGA	Vivado Hardware Manager	Vivado Hardware Manager	UG1370⁴
UltraFast Design Methodology Guide for FPGAs and SoCs (UG949). Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994). Vitis Accelerated Software Development Flow Documentation in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416). Alveo Programming Cable User Guide (UG1377).