The following figure shows the clocks generated and connected to the FPGA. Detailed FPGA, clock pin connections, and frequencies are documented in the Alveo U50/U50LV accelerator card XDC file.
Figure 1. Alveo U50/U50LV Clocking
The following figure shows the clocks generated and connected to the FPGA. Detailed FPGA, clock pin connections, and frequencies are documented in the Alveo U50/U50LV accelerator card XDC file.