[Figure 1, callout 5]
The VCK190 U1 XCVC1902 bank 500 PMC_MIO[0:12] pins are connected to the 240-pin (8 x 30) MIO connector J212. This interface enables high-speed XCVC1902 configuration using the X-EBM-01 QSPI external mezzanine card installed on J212.
The detailed adaptive SoC connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Xilinx Design Constraints. The XCVC1902 MIO connector J212 pinout is listed in the following figure.
Figure 1. MIO Connector J212 Pinout
