Parameterized Macro: NOC Slave Unit with stream interface
- MACRO_GROUP: XPM
- MACRO_SUBGROUP: XPM_NOC
Introduction
This macro is used to instantiate NOC Slave Unit with stream interface
Additionl content can go here.
Port Descriptions
Port | Direction | Width | Domain | Sense | Handling if Unused | Function |
---|---|---|---|---|---|---|
m_axis_aclk | Input | 1 | NA | EDGE_RISING | Active | AXI Interface master clock Clock signal. All inputs/outputs of this bus interface are rising edge aligned with this clock. |
m_axis_tdata | Output | DATA_WIDTH | NA | NA | Active | AXI interface transmit data m_axis_tdata is the primary payload that is used to provide the data that is passing across the interface |
m_axis_tdest | Output | DST_ID_WIDTH | NA | NA | Active | AXI interface TDEST m_axis_tdesk provides routing information for the data stream |
m_axis_tid | Output | ID_WIDTH | NA | NA | Active | AXI interface transmit id m_asix_tid is the data stream identifier that indicates different streams of data |
m_axis_tkeep | Output | DATA_WIDTH / 8 | NA | NA | Active | AXI interface transmit tkeep m_asix_tkeep is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as part of the data stream. |
m_axis_tlast | Output | 1 | NA | NA | Active | AXI interface transmit tlast m_axis_tlast indicates the boundary of a packet |
m_axis_tready | Input | 1 | NA | NA | Active | AXI interface transmit ready signal m_asix_tready indicates that the slave can accept a transfer in the current cycle. |
m_axis_tvalid | Output | 1 | NA | NA | Active | AXI interface transmit tvalid m_axis_tvalid indicates that the master is driving a valid transfer. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
DATA_WIDTH | DECIMAL | 512, 128, 256 | 512 | AXI channel Data width Allowd value 128,256,512 Default value = 512 |
DST_ID_WIDTH | DECIMAL | 1 to 10 | 4 | AXI Channel DST port width Allowed values 1 to 10. Default value = 4 |
ID_WIDTH | DECIMAL | 1 to 6 | 6 | AXI Channel ID port width Allowed values 1 to 6. Default value = 6 |
NOC_FABRIC | STRING | String | "pl" | Choosing the PL NMU of the given device |
VHDL Instantiation Template
Unless they already exist, copy the
following two statements and paste them before the entity declaration.
Library xpm;
use xpm.vcomponents.all;
-- xpm_nsu_strm: NSU_STRM
-- Xilinx Parameterized Macro, version 2024.2
xpm_nsu_strm_inst : xpm_nsu_strm
generic map (
NOC_FABRIC => "pl", -- pl
DATA_WIDTH => 512, -- 128/256/512
ID_WIDTH => 6, -- 1 to 6
DST_ID_WIDTH => 4 -- 1 to 10
) port map (
m_axis_aclk => m_axis_aclk,
m_axis_tid => m_axis_tid,
m_axis_tdata => m_axis_tdata,
m_axis_tkeep => m_axis_tkeep,
m_axis_tlast => m_axis_tlast,
m_axis_tvalid => m_axis_tvalid,
m_axis_tdest => m_axis_tdest,
m_axis_tready => m_axis_tready
);
-- End of xpm_nsu_strm_inst instantiation
Verilog Instantiation Template
// xpm_nsu_strm: NSU_STRM
// Xilinx Parameterized Macro, version 2024.2
xpm_nsu_strm # (
.NOC_FABRIC("pl"), // pl
.DATA_WIDTH(512), // 128/256/512
.ID_WIDTH(6), // 1 to 6
.DST_ID_WIDTH (4) //1 to 10
) xpm_nsu_strm_inst
(
.m_axis_aclk(m_axis_aclk),
.m_axis_tid(m_axis_tid),
.m_axis_tdata( m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tready(m_axis_tready)
);
// End of xpm_nsu_strm_inst instantiation