XPM_NMU_STRM - 2024.2 English - UG1353

Versal Architecture AI Core Series Libraries Guide (UG1353)

Document ID
UG1353
Release Date
2024-11-13
Version
2024.2 English

Parameterized Macro: NOC Master Unit with stream interface

  • MACRO_GROUP: XPM
  • MACRO_SUBGROUP: XPM_NOC

Introduction

This macro is used to instantiate NOC Master Unit with stream interface

Additionl content can go here.

Port Descriptions

Port Direction Width Domain Sense Handling if Unused Function
dst_id_err Output 1 NA NA Active
s_axis_aclk Input 1 NA EDGE_RISING Active AXI Interface master clock Clock signal. All inputs/outputs of this bus interface are rising edge aligned with this clock.
s_axis_tdata Input DATA_WIDTH NA NA Active AXI interface transmit data s_axis_tdata is the primary payload that is used to provide the data that is passing across the interface
s_axis_tdest Input DST_ID_WIDTH NA NA Active AXI interface TDEST s_axis_tdesk provides routing information for the data stream
s_axis_tid Input ID_WIDTH NA NA Active AXI interface transmit id s_asix_tid is the data stream identifier that indicates different streams of data
s_axis_tkeep Input DATA_WIDTH / 8 NA NA Active AXI interface transmit tkeep s_asix_tkeep is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as part of the data stream.
s_axis_tlast Input 1 NA NA Active AXI interface transmit tlast s_axis_tlast indicates the boundary of a packet
s_axis_tready Output 1 NA NA Active AXI interface transmit ready signal s_asix_tready indicates that the slave can accept a transfer in the current cycle.
s_axis_tvalid Input 1 NA NA Active AXI interface transmit tvalid s_axis_tvalid indicates that the master is driving a valid transfer.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
DATA_WIDTH DECIMAL 512, 128, 256 512 AXI channel Data width Allowd value 128,256,512 Default value = 512
DST_ID_WIDTH DECIMAL 1 to 10 4 AXI Channel DST port width Allowed values 1 to 10. Default value = 4
ID_WIDTH DECIMAL 1 to 16 16 AXI Channel ID port width Allowed values 1 to 16. Default value = 16
NOC_FABRIC STRING String "pl" Choosing the PL NMU of the given device

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library xpm;
use xpm.vcomponents.all;

-- xpm_nmu_strm: NMU_STRM
-- Xilinx Parameterized Macro, version 2024.2

xpm_nmu_strm_inst : xpm_nmu_strm
generic map (
		NOC_FABRIC => "pl",		-- pl
		DATA_WIDTH => 512,		-- 128/256/512
		ID_WIDTH => 16,			-- 1 to 16
		DST_ID_WIDTH => 4		-- 1 to 10
)
port map (
	s_axis_aclk => s_axis_aclk,
	s_axis_tid => s_axis_tid,
	s_axis_tdata => s_axis_tdata,
	s_axis_tkeep => s_axis_tkeep,
	s_axis_tlast => s_axis_tlast,
	s_axis_tvalid => s_axis_tvalid,
	s_axis_tready => s_axis_tready,
	s_axis_tdest => s_axis_tdest,
	dst_id_err => dst_id_err
);

-- End of xpm_nmu_strm_inst instantiation

Verilog Instantiation Template


// xpm_nmu_strm: NMU_STRM
// Xilinx Parameterized Macro, version 2024.2

xpm_nmu_strm #(
	.NOC_FABRIC("pl"),	//pl
	.DATA_WIDTH(512),	//128/256/512
	.ID_WIDTH(16),		// 1 to 16
     .DST_ID_WIDTH(4)	//1 to 10
)
xpm_nmu_strm_inst (
		.s_axis_aclk(s_axis_aclk) ,
          	.s_axis_tid(s_axis_tid),
	     	.s_axis_tdata(s_axis_tdata),
	    	.s_axis_tkeep(s_axis_tkeep),
	     	.s_axis_tlast(s_axis_tlast),
		.s_axis_tvalid(s_axis_tvalid),
		.s_axis_tready(s_axis_tready),
		.s_axis_tdest(s_axis_tdest),
		.dst_id_err(dst_id_err)
);

// End of xpm_nmu_strm_inst instantiation