XPM_MEMORY_DPROM - XPM_MEMORY_DPROM - 2026.1 English - Parameterized Macro: Dual Port ROM

Parameterized Macro: Dual Port ROM

MACRO_GROUP: XPM
MACRO_SUBGROUP: XPM_MEMORY

Introduction

This macro instantiates True Dual Port ROM. Port A and Port B simultaneously perform read operations from the memory.

The following describes the basic read and write port usage of an XPM_MEMORY instance. It does not distinguish between ports A and B.

All synchronous signals are sensitive to the rising edge of clk[a|b], assumed to be a buffered and toggling clock signal behaving according to target device and memory primitive requirements.
A read operation is performed implicitly on address addr[a|b] combinatorially. The data output registers on each clk[a|b] cycle when en[a|b] is asserted.
Read data appears on the dout[a|b] port READ_LATENCY_[A|B] clk[a|b] cycles after the associated read operation.
The value of en[a|b] gates all read operations on the initiating clk[a|b] cycle, regardless of input or output latencies.
When rst[a|b] is asserted on a clk[a|b] cycle, the final output register resets immediately but synchronously to READ_RESET_VALUE_[A|B], irrespective of READ_LATENCY_[A|B].
When regce[a|b] is asserted and rst[a|b] is de-asserted on a clk[a|b] cycle, the final output register captures and outputs the value from the previous pipeline register.
Undriven or unknown values provided on module inputs produce undefined memory array and output port behavior.
Using MEMORY INIT PARAM limits the maximum supported memory size to 4K bits.
For better timing performance in larger memories (>1 Mb), use CASCADE_HEIGHT of 1 with sufficient read latencies.
WRITE_MODE_A must be set to “read_first” in Dual Port ROM configurations. Violating this results in a DRC error.

Note:

When the attribute “CLOCKING_MODE” is set to “common_clock”, all read/write operations to memory through port A and port B are performed on clka. If this attribute is set to “independent_clock”, then read/write operations through port A are performed based on clka, and read/write operations through port B are performed based on clkb.
set_false_path constraint is needed for the independent clock distributed RAM based memory if the design takes care of avoiding address collision (write address != read address at any given point of time).
For larger memories (≥2 MB), use a read latency > 8 because the default cascade height used by Vivado synthesis is 8.

Timing Diagrams

Note: The preceding waveforms do not distinguish between port A and port B. The behavior shown in the waveforms is true for both port A and port B.

Port Descriptions

Port	Direction	Width	Domain	Sense	Handling if Unused	Function
addra	Input	ADDR_WIDTH_A	clka	NA	Active	Address for port A read operations.
addrb	Input	ADDR_WIDTH_B	clkb	NA	Active	Address for port B read operations.
clka	Input	1	NA	EDGE_RISING	Active	Clock signal for port A. Also clocks port B when parameter CLOCKING_MODE is "common_clock".
clkb	Input	1	NA	EDGE_RISING	Active	Clock signal for port B when parameter CLOCKING_MODE is "independent_clock". Unused when parameter CLOCKING_MODE is "common_clock".
dbiterra	Output	1	clka	LEVEL_HIGH	DoNotCare	Leave open.
dbiterrb	Output	1	clkb	LEVEL_HIGH	DoNotCare	Leave open.
douta	Output	READ_DATA_WIDTH_A	clka	NA	Active	Data output for port A read operations.
doutb	Output	READ_DATA_WIDTH_B	clkb	NA	Active	Data output for port B read operations.
ena	Input	1	clka	LEVEL_HIGH	Active	Memory enable signal for port A. Must be high on the clock cycles when you initiate read operations. Pipelined internally.
enb	Input	1	clkb	LEVEL_HIGH	Active	Memory enable signal for port B. Must be high on the clock cycles when you initiate read operations. Pipelined internally.
injectdbiterra	Input	1	clka	LEVEL_HIGH	0	Do not change from the provided value.
injectdbiterrb	Input	1	clkb	LEVEL_HIGH	0	Do not change from the provided value.
injectsbiterra	Input	1	clka	LEVEL_HIGH	0	Do not change from the provided value.
injectsbiterrb	Input	1	clkb	LEVEL_HIGH	0	Do not change from the provided value.
regcea	Input	1	clka	LEVEL_HIGH	1	Do not change from the provided value.
regceb	Input	1	clkb	LEVEL_HIGH	1	Do not change from the provided value.
rsta	Input	1	clka	LEVEL_HIGH	Active	Reset signal for the final port A output register stage. Synchronously resets output port douta to the value specified by parameter READ_RESET_VALUE_A.
rstb	Input	1	clkb	LEVEL_HIGH	Active	Reset signal for the final port B output register stage. Synchronously resets output port doutb to the value specified by parameter READ_RESET_VALUE_B.
sbiterra	Output	1	clka	LEVEL_HIGH	DoNotCare	Leave open.
sbiterrb	Output	1	clkb	LEVEL_HIGH	DoNotCare	Leave open.
sleep	Input	1	NA	LEVEL_HIGH	0	sleep signal to enable the dynamic power saving feature.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
ADDR_WIDTH_A	DECIMAL	1 to 20	6	Specify the width of the port A address port addra, in bits. Must be large enough to access the entire memory from port A, that is, >= $clog2(MEMORY_SIZE/READ_DATA_WIDTH_A).
ADDR_WIDTH_B	DECIMAL	1 to 20	6	Specify the width of the port B address port addrb, in bits. Must be large enough to access the entire memory from port B, that is, >= $clog2(MEMORY_SIZE/READ_DATA_WIDTH_B).
AUTO_SLEEP_TIME	DECIMAL	0 to 15	0	You must set this parameter to 0. 0: Disable auto sleep feature
CASCADE_HEIGHT	DECIMAL	0 to 64	0	0: No Cascade Height: Enables Vivado Synthesis to choose. 1 or more - Vivado Synthesis sets the specified value as Cascade Height.
CLOCKING_MODE	STRING	"common_clock", "independent_clock"	"common_clock"	Specifies whether port A and port B use a common clock or independent clocks. "common_clock": Common clocking; Clock both port A and port B with clka "independent_clock": Independent clocking; clock port A with clka and port B with clkb
ECC_BIT_RANGE	STRING	String	"7:0"	This parameter is only used by synthesis. Specify the ECC bit range on the provided data. "7:0": Specifies lower 8 bits are ECC bits.
ECC_MODE	STRING	"no_ecc", "both_encode_and_decode", "decode_only", "encode_only"	"no_ecc"	"no_ecc": Disables ECC "encode_only": Enables ECC Encoder only "decode_only": Enables ECC Decoder only "both_encode_and_decode": Enables both ECC Encoder and Decoder
ECC_TYPE	STRING	"none", "ECCHSIAO32-7", "ECCHSIAO64-8", "ECCHSIAO128-9", "ECCH32-7", "ECCH64-8"	"none"	This parameter is only used by synthesis. Specify the algorithm used to generate the ecc bits outside the XPM Memory. XPM Memory does not performs ECC operation with this parameter. When ECC_MODE is not equal to no_ecc, the macro ignores the ECC_TYPE parameter and sets its value to none. "none": No ECC "ECCH32-7": Uses 32 bit ECC Hamming algorithm "ECCH64-8": Uses 64 bit ECC Hamming algorithm "ECCHSIAO32-7": Uses 32 bit ECC HSIAO algorithm "ECCHSIAO64-8": Uses 64 bit ECC HSIAO algorithm "ECCHSIAO128-9": Uses 128 bit ECC HSIAO algorithm
IGNORE_INIT_SYNTH	DECIMAL	0 to 1	0	0: Initiazation file if specified applies for both simulation and synthesis 1: Initiazation file if specified applies for only simulation and ignored for synthesis
MEMORY_INIT_FILE	STRING	String	"none"	Specify "none" (including quotes) for no memory initialization, or specify the name of a memory initialization file. Enter only the name of the file with .mem extension, including quotes but without path (for example, "my_file.mem"). File format must be ASCII and consist of only hexadecimal values organized into the specified depth by narrowest data width generic value of the memory. Initialization of memory happens through the file name specified only when parameter MEMORY_INIT_PARAM value is equal to "". \| When using XPM_MEMORY in a project, add the specified file to the Vivado project as a design source.
MEMORY_INIT_PARAM	STRING	String	"0"	Specify "" or "0" (including quotes) for no memory initialization through parameter, or specify the string containing the hex characters. Enter only hex characters with each location separated by delimiter (,). Parameter format must be ASCII and consist of only hexadecimal values organized into the specified depth by narrowest data width generic value of the memory. For example, if the narrowest data width is 8, and the depth of memory is 8 locations, then pass the parameter value as follows. parameter MEMORY_INIT_PARAM = "AB,CD,EF,1,2,34,56,78" Where "AB" is the 0th location and "78" is the 7th location.
MEMORY_OPTIMIZATION	STRING	"true", "false"	"true"	Specify "true" to enable the optimization of unused memory or bits in the memory structure. Specify "false" to disable the optimization of unused memory or bits in the memory structure
MEMORY_PRIMITIVE	STRING	"auto", "block", "distributed", "ultra"	"auto"	Specifies the memory primitive (resource type) to use. "auto": Enables Vivado Synthesis to choose "distributed": Distributed memory "block": Block memory
MEMORY_SIZE	DECIMAL	2 to 150994944	2048	Specify the total memory array size, in bits. For example, enter 65536 for a 2kx32 ROM.
MESSAGE_CONTROL	DECIMAL	0 to 1	0	Specify 1 to enable the dynamic message reporting such as collision warnings, and 0 to disable the message reporting
RAM_DECOMP	STRING	"auto", "area", "power"	"auto"	Specifies the decomposition of the memory. "auto": Synthesis selects default. "power": Synthesis selects a strategy to reduce switching activity of RAMs and maps using widest configuration possible. "area": Synthesis selects a strategy to reduce RAM resource count.
READ_DATA_WIDTH_A	DECIMAL	1 to 4608	32	Specify the width of the port A read data output port douta, in bits.
READ_DATA_WIDTH_B	DECIMAL	1 to 4608	32	Specify the width of the port B read data output port doutb, in bits.
READ_LATENCY_A	DECIMAL	0 to 100	2	Specify the number of register stages in the port A read data pipeline. Read data output to port douta takes this number of clka cycles. Targeting block memory requires a value of 1 or larger. 1 causes use of memory latch only; 2 causes use of output register. Targeting distributed memory requires a value of 0 or larger. 0 indicates combinatorial output. Values larger than 2 synthesize additional flip-flops that are not retimed into memory primitives.
READ_LATENCY_B	DECIMAL	0 to 100	2	Specify the number of register stages in the port B read data pipeline. Read data output to port doutb takes this number of clkb cycles (clka when CLOCKING_MODE is "common_clock"). Targeting block memory requires a value of 1 or larger, 1 causes use of memory latch only; 2 causes use of output register. Targeting distributed memory requires a value of 0 or larger, 0 indicates combinatorial output. Values larger than 2 synthesize additional flip-flops that are not retimed into memory primitives.
READ_RESET_VALUE_A	STRING	String	"0"	Specify the reset value of the port A final output register stage in response to rsta input port assertion. For example, to reset the value of port douta to all 0s when READ_DATA_WIDTH_A is 32, specify 32HHHHh0.
READ_RESET_VALUE_B	STRING	String	"0"	Specify the reset value of the port B final output register stage in response to rstb input port assertion.
RST_MODE_A	STRING	"SYNC", "ASYNC"	"SYNC"	Describes the behavior of the reset. "SYNC": when you apply reset, it synchronously resets output port douta to the value specified by parameter READ_RESET_VALUE_A "ASYNC": when you apply reset, it asynchronously resets output port douta to zero
RST_MODE_B	STRING	"SYNC", "ASYNC"	"SYNC"	Describes the behavior of the reset "SYNC": When you apply reset, it synchronously resets output port doutb to the value specified by parameter READ_RESET_VALUE_B "ASYNC": When you apply reset, it asynchronously resets output port doutb to zero
SIM_ASSERT_CHK	DECIMAL	0 to 1	0	0: Disable simulation message reporting. This does not report messages related to potential misuse. 1: Enable simulation message reporting. This reports messages related to potential misuse.
USE_MEM_INIT	DECIMAL	0 to 1	1	Specify 1 to enable the generation of the following message and 0 to disable generation of the following message completely. "INFO - MEMORY_INIT_FILE and MEMORY_INIT_PARAM together specifies no memory initialization. Initial memory contents will be all 0s." NOTE: The tool generates this message only when there is no Memory Initialization specified either through file or Parameter.
USE_MEM_INIT_MMI	DECIMAL	0 to 1	0	Specify 1 to expose this memory information for writing to the MMI file.
WAKEUP_TIME	STRING	"disable_sleep", "use_sleep_pin"	"disable_sleep"	Specify "disable_sleep" to disable dynamic power saving option, and specify "use_sleep_pin" to enable the dynamic power saving option

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library xpm;
use xpm.vcomponents.all;


-- xpm_memory_dprom: Dual Port ROM
-- Xilinx Parameterized Macro, version 2026.1

xpm_memory_dprom_inst : xpm_memory_dprom
generic map (
   ADDR_WIDTH_A => 6,               -- DECIMAL
   ADDR_WIDTH_B => 6,               -- DECIMAL
   AUTO_SLEEP_TIME => 0,            -- DECIMAL
   CASCADE_HEIGHT => 0,             -- DECIMAL
   CLOCKING_MODE => "common_clock", -- String
   ECC_BIT_RANGE => "7:0",          -- String
   ECC_MODE => "no_ecc",            -- String
   ECC_TYPE => "none",              -- String
   IGNORE_INIT_SYNTH => 0,          -- DECIMAL
   MEMORY_INIT_FILE => "none",      -- String
   MEMORY_INIT_PARAM => "0",        -- String
   MEMORY_OPTIMIZATION => "true",   -- String
   MEMORY_PRIMITIVE => "auto",      -- String
   MEMORY_SIZE => 2048,             -- DECIMAL
   MESSAGE_CONTROL => 0,            -- DECIMAL
   RAM_DECOMP => "auto",            -- String
   READ_DATA_WIDTH_A => 32,         -- DECIMAL
   READ_DATA_WIDTH_B => 32,         -- DECIMAL
   READ_LATENCY_A => 2,             -- DECIMAL
   READ_LATENCY_B => 2,             -- DECIMAL
   READ_RESET_VALUE_A => "0",       -- String
   READ_RESET_VALUE_B => "0",       -- String
   RST_MODE_A => "SYNC",            -- String
   RST_MODE_B => "SYNC",            -- String
   SIM_ASSERT_CHK => 0,             -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
   USE_MEM_INIT => 1,               -- DECIMAL
   USE_MEM_INIT_MMI => 0,           -- DECIMAL
   WAKEUP_TIME => "disable_sleep"   -- String
)
port map (
   sleep => sleep, -- 1-bit input: sleep signal to enable the dynamic power saving feature.
   clka => clka, -- 1-bit input: Clock signal for port A. Also clocks port B when parameter CLOCKING_MODE is "common_clock".
   rsta => rsta, -- 1-bit input: Reset signal for the final port A output register stage. Synchronously resets output port
                                     -- douta to the value specified by parameter READ_RESET_VALUE_A.

   ena => ena, -- 1-bit input: Memory enable signal for port A. Must be high on the clock cycles when you initiate read
                                     -- operations. Pipelined internally.

   regcea => regcea, -- 1-bit input: Do not change from the provided value.
   addra => addra, -- ADDR_WIDTH_A-bit input: Address for port A read operations.
   injectsbiterra => injectsbiterra, -- 1-bit input: Do not change from the provided value.
   injectdbiterra => injectdbiterra, -- 1-bit input: Do not change from the provided value.
   douta => douta, -- READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
   sbiterra => sbiterra, -- 1-bit output: Leave open.
   dbiterra => dbiterra, -- 1-bit output: Leave open.
   clkb => clkb, -- 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is "independent_clock". Unused when
                                     -- parameter CLOCKING_MODE is "common_clock".

   rstb => rstb, -- 1-bit input: Reset signal for the final port B output register stage. Synchronously resets output port
                                     -- doutb to the value specified by parameter READ_RESET_VALUE_B.

   enb => enb, -- 1-bit input: Memory enable signal for port B. Must be high on the clock cycles when you initiate read
                                     -- operations. Pipelined internally.

   regceb => regceb, -- 1-bit input: Do not change from the provided value.
   addrb => addrb, -- ADDR_WIDTH_B-bit input: Address for port B read operations.
   injectsbiterrb => injectsbiterrb, -- 1-bit input: Do not change from the provided value.
   injectdbiterrb => injectdbiterrb, -- 1-bit input: Do not change from the provided value.
   doutb => doutb, -- READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
   sbiterrb => sbiterrb, -- 1-bit output: Leave open.
   dbiterrb => dbiterrb -- 1-bit output: Leave open.
);

-- End of xpm_memory_dprom_inst instantiation

Verilog Instantiation Template


// xpm_memory_dprom: Dual Port ROM
// Xilinx Parameterized Macro, version 2026.1

xpm_memory_dprom #(
   .ADDR_WIDTH_A(6),               // DECIMAL
   .ADDR_WIDTH_B(6),               // DECIMAL
   .AUTO_SLEEP_TIME(0),            // DECIMAL
   .CASCADE_HEIGHT(0),             // DECIMAL
   .CLOCKING_MODE("common_clock"), // String
   .ECC_BIT_RANGE("7:0"),          // String
   .ECC_MODE("no_ecc"),            // String
   .ECC_TYPE("none"),              // String
   .IGNORE_INIT_SYNTH(0),          // DECIMAL
   .MEMORY_INIT_FILE("none"),      // String
   .MEMORY_INIT_PARAM("0"),        // String
   .MEMORY_OPTIMIZATION("true"),   // String
   .MEMORY_PRIMITIVE("auto"),      // String
   .MEMORY_SIZE(2048),             // DECIMAL
   .MESSAGE_CONTROL(0),            // DECIMAL
   .RAM_DECOMP("auto"),            // String
   .READ_DATA_WIDTH_A(32),         // DECIMAL
   .READ_DATA_WIDTH_B(32),         // DECIMAL
   .READ_LATENCY_A(2),             // DECIMAL
   .READ_LATENCY_B(2),             // DECIMAL
   .READ_RESET_VALUE_A("0"),       // String
   .READ_RESET_VALUE_B("0"),       // String
   .RST_MODE_A("SYNC"),            // String
   .RST_MODE_B("SYNC"),            // String
   .SIM_ASSERT_CHK(0),             // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
   .USE_MEM_INIT(1),               // DECIMAL
   .USE_MEM_INIT_MMI(0),           // DECIMAL
   .WAKEUP_TIME("disable_sleep")   // String
)
xpm_memory_dprom_inst (
   .sleep(sleep), // 1-bit input: sleep signal to enable the dynamic power saving feature.
   .clka(clka), // 1-bit input: Clock signal for port A. Also clocks port B when parameter CLOCKING_MODE is "common_clock".
   .rsta(rsta), // 1-bit input: Reset signal for the final port A output register stage. Synchronously resets output port
                                    // douta to the value specified by parameter READ_RESET_VALUE_A.

   .ena(ena), // 1-bit input: Memory enable signal for port A. Must be high on the clock cycles when you initiate read
                                    // operations. Pipelined internally.

   .regcea(regcea), // 1-bit input: Do not change from the provided value.
   .addra(addra), // ADDR_WIDTH_A-bit input: Address for port A read operations.
   .injectsbiterra(injectsbiterra), // 1-bit input: Do not change from the provided value.
   .injectdbiterra(injectdbiterra), // 1-bit input: Do not change from the provided value.
   .douta(douta), // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
   .sbiterra(sbiterra), // 1-bit output: Leave open.
   .dbiterra(dbiterra), // 1-bit output: Leave open.
   .clkb(clkb), // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is "independent_clock". Unused when
                                    // parameter CLOCKING_MODE is "common_clock".

   .rstb(rstb), // 1-bit input: Reset signal for the final port B output register stage. Synchronously resets output port
                                    // doutb to the value specified by parameter READ_RESET_VALUE_B.

   .enb(enb), // 1-bit input: Memory enable signal for port B. Must be high on the clock cycles when you initiate read
                                    // operations. Pipelined internally.

   .regceb(regceb), // 1-bit input: Do not change from the provided value.
   .addrb(addrb), // ADDR_WIDTH_B-bit input: Address for port B read operations.
   .injectsbiterrb(injectsbiterrb), // 1-bit input: Do not change from the provided value.
   .injectdbiterrb(injectdbiterrb), // 1-bit input: Do not change from the provided value.
   .doutb(doutb), // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
   .sbiterrb(sbiterrb), // 1-bit output: Leave open.
   .dbiterrb(dbiterrb) // 1-bit output: Leave open.
);

// End of xpm_memory_dprom_inst instantiation

XPM_MEMORY_DPROM - XPM_MEMORY_DPROM - 2026.1 English - Parameterized Macro: Dual Port ROM - UG1353