XPM_CDC_SYNC_RST - XPM_CDC_SYNC_RST - 2026.1 English - Parameterized Macro: Synchronous Reset Synchronizer

Parameterized Macro: Synchronous Reset Synchronizer

MACRO_GROUP: XPM
MACRO_SUBGROUP: XPM_CDC

Introduction

This macro synchronizes a reset signal to the destination clock domain. Unlike the XPM_CDC_ASYNC_RST macro, the generated output both asserts and deasserts synchronously to the destination clock domain.

For proper operation, the destination clock must sample the input data two or more times. You can define the number of register stages that the synchronizers use and the initial value of these registers after configuration. You can also enable a simulation feature to generate messages that report any potential misuse of the macro.

Port Descriptions

Port	Direction	Width	Domain	Sense	Handling if Unused	Function
dest_clk	Input	1	NA	EDGE_RISING	Active	Destination clock.
dest_rst	Output	1	dest_clk	NA	Active	This registered output synchronizes src_rst to the destination clock domain.
src_rst	Input	1	NA	NA	Active	Source reset signal.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
DEST_SYNC_FF	DECIMAL	2 to 10	4	This parameter sets the number of register stages that synchronize the signal in the destination clock domain.
INIT	DECIMAL	1, 0	1	0: Initializes synchronization registers to 0 1: Initializes synchronization registers to 1 The option to initialize the synchronization registers means that there is no complete x-propagation behavior modeled in this macro. For complete x-propagation modeling, use the xpm_cdc_single macro.
INIT_SYNC_FF	DECIMAL	0, 1	0	0: Disable behavioral simulation initialization values on synchronization registers. 1: Enable behavioral simulation initialization values on synchronization registers.
SIM_ASSERT_CHK	DECIMAL	0, 1	0	0: Disable simulation message reporting. This does not report messages related to potential misuse. 1: Enable simulation message reporting. This reports messages related to potential misuse.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library xpm;
use xpm.vcomponents.all;


-- xpm_cdc_sync_rst: Synchronous Reset Synchronizer
-- Xilinx Parameterized Macro, version 2026.1

xpm_cdc_sync_rst_inst : xpm_cdc_sync_rst
generic map (
   DEST_SYNC_FF => 4,   -- DECIMAL; range: 2-10
   INIT => 1,           -- DECIMAL; 0=initialize synchronization registers to 0, 1=initialize synchronization registers to 1
   INIT_SYNC_FF => 0,   -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
   SIM_ASSERT_CHK => 0  -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
)
port map (
   src_rst => src_rst, -- 1-bit input: Source reset signal.
   dest_clk => dest_clk, -- 1-bit input: Destination clock.
   dest_rst => dest_rst -- 1-bit output: This registered output synchronizes src_rst to the destination clock domain.
);

-- End of xpm_cdc_sync_rst_inst instantiation

Verilog Instantiation Template


// xpm_cdc_sync_rst: Synchronous Reset Synchronizer
// Xilinx Parameterized Macro, version 2026.1

xpm_cdc_sync_rst #(
   .DEST_SYNC_FF(4),   // DECIMAL; range: 2-10
   .INIT(1),           // DECIMAL; 0=initialize synchronization registers to 0, 1=initialize synchronization registers to 1
   .INIT_SYNC_FF(0),   // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
   .SIM_ASSERT_CHK(0)  // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
)
xpm_cdc_sync_rst_inst (
   .src_rst(src_rst), // 1-bit input: Source reset signal.
   .dest_clk(dest_clk), // 1-bit input: Destination clock.
   .dest_rst(dest_rst) // 1-bit output: This registered output synchronizes src_rst to the destination clock domain.
);

// End of xpm_cdc_sync_rst_inst instantiation

Related Information

XPM CDC Testbench File (xpm-cdc-testbench.zip)

XPM_CDC_SYNC_RST - XPM_CDC_SYNC_RST - 2026.1 English - Parameterized Macro: Synchronous Reset Synchronizer - UG1353