XPM_NSU_STRM_SV - 2025.2 English - Parameterized Macro: AXI Streaming (AXI Full) NOC Slave Unit

Parameterized Macro: AXI Streaming (AXI Full) NOC Slave Unit

MACRO_GROUP: XPM
MACRO_SUBGROUP: NOC

Introduction

This macro is used to instantiate AXI Streaming (AXI Full) NOC Slave Unit.

Port Descriptions

Port	Direction	Width	Domain	Sense	Handling if Unused	Function
m_axis_aclk	Input	1	NA	EDGE_RISING	Active	Master Interface Clock: All signals on slave interface are sampled on the rising edge of this clock.
M_AXIS	Interface					Master AXI-Stream interface.

Module Ports

The vivado_interfaces.svh file includes the following module ports for AXI4, AXI4-Stream, and AXI4-Lite interfaces.

Interface Type	Ports
vivado_axis_v1_0	TID, TDEST, TDATA, TSTRB, TKEEP, TLAST, TUSER, TVALID, TREADY
vivado_aximm_v1_0	AWID, AWADDR, AWLEN, AWSIZE, AWBURST, AWLOCK, AWCACHE, AWPROT, AWREGION, AWQOS, AWUSER, AWVALID, WID, WDATA, WSTRB, WLAST, WUSER, WVALID, BREADY, ARID, ARADDR, ARLEN, ARSIZE, ARBURST, ARLOCK, ARCACHE, ARPROT, ARREGION, ARQOS, ARUSER, ARVALID, RREADY, AWREADY, WREADY, BID, BRESP, BUSER, BVALID, ARREADY, RID, RDATA, RRESP, RLAST, RUSER, RVALID
vivado_axi4_lite_v1_0	AWADDR, AWPROT, AWVALID, WDATA, WSTRB, WVALID, BREADY, ARADDR, ARPROT, ARVALID, RREADY, AWREADY, WREADY, BRESP, BVALID, ARREADY, RDATA, RRESP, RVALID

Note: The parameter values passed to the interfaces must match the port mapping in the module instantiations.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
DATA_WIDTH	DECIMAL	512, 128, 256	512	Defines the width of the DATA ports, s_axi_rdata, s_axi_wdata.
DST_ID_WIDTH	DECIMAL	0 to 4	4	Defines the width of the TDEST port
ID_WIDTH	DECIMAL	0 to 6	6	Defines the width of the ID ports, TID
NOC_FABRIC	STRING	"VNOC", "BLI", "pl", "pl_hbm"	"VNOC"	"VNOC"/"pl" - Choosing the VNOC NMU of given device "BLI"/"pl_hbm" - Disables Packet FIFO mode

System Verilog Instantiation Template

// xpm_nsu_strm_sv    : In order to incorporate this function into the design,
//  System Verilog    : the following instance declaration needs to be placed
//   instance         : in the body of the design code.  The instance name
// declaration        : (xpm_nsu_strm_inst) and/or the port declarations within the
//     code           : parenthesis may be changed to properly reference and
//                    : connect this function to the design.  All inputs
//                    : and outputs must be connected.

// -------------- Begin Cut here for INTERFACE Include ------- // INCLUDE_TAG
`include "vivado_interfaces.svh" 
// -- INCLUDE_TAG_END ------ End INTERFACE Include ------------

// -------------- Begin Cut here for INTERFACE Template ------- // INTF_TAG 
// Default parameter used by the module are for S_AXI
vivado_axis_v1_0 #(
    .TDATA_NUM_BYTES(1),
    .TDEST_WIDTH(4),
    .TID_WIDTH(6)
) M_AXIS();
//  -- INTF_TAG_END -------------- End INTERFACE Template ------------------ 

//  <-----Cut code below this line---->
// xpm_nsu_strm_sv: AXI Streaming (AXI Full) NOC Slave Unit
// Xilinx Parameterized Macro, version 2025.2

xpm_nsu_strm_sv #(
    .DATA_WIDTH(TDATA_NUM_BYTES*8),  // DECIMAL
    .DST_ID_WIDTH(TDEST_WIDTH),          // DECIMAL
    .ID_WIDTH(TID_WIDTH),                // DECIMAL
    .NOC_FABRIC("VNOC")                 // STRING
)
xpm_nsu_strm_sv_inst (
    .m_axis_aclk(m_axis_aclk),          // 1-bit input: Master Interface Clock: All signals on slave interface are sampled on the rising edge of this
                                       // clock.
    .M_AXIS(M_AXIS.master)
);

// End of xpm_nsu_strm_inst instantiation