XPM_NSU_MM_SV - 2025.2 English - Parameterized Macro: AXI Memory Mapped (AXI Full) NOC Slave Unit

Parameterized Macro: AXI Memory Mapped (AXI Full) NOC Slave Unit

MACRO_GROUP: XPM
MACRO_SUBGROUP: NOC

Introduction

This macro is used to instantiate AXI Memory Mapped (AXI Full) NOC Slave Unit.

Module Ports

The vivado_interfaces.svh file includes the following module ports for AXI4, AXI4-Stream, and AXI4-Lite interfaces.

Interface Type	Ports
vivado_axis_v1_0	TID, TDEST, TDATA, TSTRB, TKEEP, TLAST, TUSER, TVALID, TREADY
vivado_aximm_v1_0	AWID, AWADDR, AWLEN, AWSIZE, AWBURST, AWLOCK, AWCACHE, AWPROT, AWREGION, AWQOS, AWUSER, AWVALID, WID, WDATA, WSTRB, WLAST, WUSER, WVALID, BREADY, ARID, ARADDR, ARLEN, ARSIZE, ARBURST, ARLOCK, ARCACHE, ARPROT, ARREGION, ARQOS, ARUSER, ARVALID, RREADY, AWREADY, WREADY, BID, BRESP, BUSER, BVALID, ARREADY, RID, RDATA, RRESP, RLAST, RUSER, RVALID
vivado_axi4_lite_v1_0	AWADDR, AWPROT, AWVALID, WDATA, WSTRB, WVALID, BREADY, ARADDR, ARPROT, ARVALID, RREADY, AWREADY, WREADY, BRESP, BVALID, ARREADY, RDATA, RRESP, RVALID

Note: The parameter values passed to the interfaces must match the port mapping in the module instantiations.

Port Descriptions

Port	Direction	Width	Domain	Sense	Handling if Unused	Function
M_AXI	Interface					Master AXI interface.
m_axi_aclk	Input	1	NA	EDGE_RISING	Active	Master Interface Clock: All signals on slave interface are sampled on the rising edge of this clock.
nsu_firewall_err	Output	1	m_axi_aclk	LEVEL_HIGH	Active	Indicates that firewall error occurred during write or read transaction.
nsu_usr_interrupt_in	Input	1	m_axi_aclk	LEVEL_HIGH	Active	User interrupt signal .

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
ADDR_WIDTH	DECIMAL	12 to 64	64	Defines the width of the ADDR ports, s_axi_araddr, s_axi_awaddr
AUSER_WIDTH	DECIMAL	16, 18	16	Defines the width of the Address USER ports, s_axi_aruser, s_axi_awuser
DATA_WIDTH	DECIMAL	512, 32, 64, 128, 256	512	Defines the width of the DATA ports, s_axi_rdata, s_axi_wdata.
DUSER_WIDTH	DECIMAL	128, 0	128	Defines the width of the Data USER ports, s_axi_ruser, s_axi_wuser
ENABLE_FIREWALL	STRING	"false", "true"	"false"	"false" - Firewall feature is disabled "true" - Firewall feature is enabled NOTE: The Firewall feature is only availale for NOC2 devices
ENABLE_USR_INTERRUPT	STRING	"false", "true"	"false"	"true" - Enable user interrupt functionality "false" - Disable user interrupt functionality
ID_WIDTH	DECIMAL	2 to 2	2	Defines the width of the ID ports, s_axi_arid, s_axi_awid, s_axi_wid, s_axi_rid
NOC_FABRIC	STRING	"VNOC", "BLI", "pl", "pl_hbm"	"VNOC"	"VNOC"/"pl" - Choosing the VNOC NMU of given device "BLI"/"pl_hbm" - Disables Packet FIFO mode
SIDEBAND_PINS	STRING	"false", "true"	"false"	"true" - Drive AXI sideband parity signals over Address and Data User ports "addr" - Drive AXI sideband parity signals over Address User ports "data" - Drive AXI sideband parity signals over Data User ports "false" - Disable driving AXI sideband parity signals over Address or Data User ports

System Verilog Instantiation Template

// xpm_nsu_mm_sv     : In order to incorporate this function into the design,
//  System Verilog   : the following instance declaration needs to be placed
//  instance         : in the body of the design code.  The instance name
// declaration       : (xpm_nsu_mm_sv_inst) and/or the port declarations within the
//    code           : parenthesis may be changed to properly reference and
//                   : connect this function to the design.  All inputs
//                   : and outputs must be connected.

//  Please reference the appropriate libraries guide for additional information on the XPM modules.
// -------------- Begin Cut here for INTERFACE Include ------- // INCLUDE_TAG
`include "vivado_interfaces.svh" 
// -- INCLUDE_TAG_END ------ End INTERFACE Include ------------

// -------------- Begin Cut here for INTERFACE Template ------- // INTF_TAG 
// Default parameter used by the module are for S_AXI
vivado_aximm_v1_0 #(
    .ID_WIDTH(1),
    .ADDR_WIDTH(32),
    .AWUSER_WIDTH(16),
    .DATA_WIDTH(32),
    .WUSER_WIDTH(4),
    .BUSER_WIDTH(16),
    .ARUSER_WIDTH(16),
    .RUSER_WIDTH(4)
) M_AXI();
//  -- INTF_TAG_END -------------- End INTERFACE Template ------------------ 

//  <-----Cut code below this line---->
// xpm_nsu_mm_sv: AXI Memory Mapped (AXI Full) NOC Slave Unit
// Xilinx Parameterized Macro, version 2025.2

xpm_nsu_mm_sv #(
    .ADDR_WIDTH(ADDR_WIDTH),              // DECIMAL
    .AUSER_WIDTH(AWUSER_WIDTH),           // DECIMAL
    .DATA_WIDTH(DATA_WIDTH),              // DECIMAL
    .ID_WIDTH(ID_WIDTH),                  // DECIMAL
    .DUSER_WIDTH(WUSER_WIDTH),            // DECIMAL
    .ENABLE_FIREWALL("false"),            // STRING
    .ENABLE_USR_INTERRUPT("false"),       // STRING
    .NOC_FABRIC("VNOC"),                  // STRING
    .SIDEBAND_PINS("false")               // STRING
)
xpm_nsu_mm_sv_inst (
    .m_axi_aclk(m_axi_aclk),                     // 1-bit input: Master Interface Clock: All signals on slave interface are sampled on the rising
                                                 // edge of this clock.
    .M_AXI(M_AXI.master),
    .nsu_firewall_err(nsu_firewall_err),         // 1-bit output: Indicates that firewall error occurred during write or read transaction
    .nsu_usr_interrupt_in(nsu_usr_interrupt_in)  // 4-bit input: User interrupt signal
);

// End of xpm_nsu_mm_sv_inst instantiation