Parameterized Macro: Synchronous FIFO
- MACRO_GROUP: XPM
- MACRO_SUBGROUP: XPM_FIFO
Introduction
This macro is used to instantiate synchronous FIFO.
The following describes the basic write and read operation
of an XPM_FIFO instance.
- All synchronous signals are sensitive to the rising edge of wr_clk, which is assumed to be a buffered and toggling clock signal behaving according to target device and FIFO/memory primitive requirements.
- A write operation is performed when the FIFO is not full and wr_en is asserted on each wr_clk cycle.
- A read operation is performed when the FIFO is not empty and rd_en is asserted on each wr_clk cycle.
- The number of clock cycles required for XPM FIFO to react to dout,
full and empty changes depends on the CLOCK_DOMAIN, READ_MODE, and
FIFO_READ_LATENCY settings.
- It might take more than one wr_clk cycle to deassert empty due to write operation (wr_en = 1).
- It might take more than one wr_clk cycle to present the read data on dout port upon assertion of rd_en.
- It might take more than one wr_clk cycle to deassert full due to read operation (rd_en = 1).
- All write operations are gated by the value of wr_en and full on the initiating wr_clk cycle.
- All read operations are gated by the value of rd_en and empty on the initiating wr_clk cycle.
- Undriven or unknown values provided on module inputs will produce undefined output port behavior.
- wr_en/rd_en should not be toggled when reset (rst) or wr_rst_busy or rd_rst_busy is asserted.
- Assertion/deassertion of prog_full happens only when full is deasserted.
- Assertion/deassertion of prog_empty happens only when empty is deasserted.
Timing Diagrams
Figure 1. Reset Behavior
Figure 2. Standard Write Operation. FIFO_WRITE_DEPTH=16, PROG_FULL_THRESH=6
Figure 3. Standard Read Operation. FIFO_WRITE_DEPTH=16, PROG_EMPTY_THRESH=3, FIFO_READ_LATENCY=1
Figure 4. Standard Read Operation. FIFO_WRITE_DEPTH=16, PROG_EMPTY_THRESH=3, FIFO_READ_LATENCY=3
Figure 5. Write Operation. READ_MODE=FWFT, FIFO_WRITE_DEPTH=16, PROG_FULL_THRESH=7
Figure 6. Read Operation. READ_MODE=FWFT, FIFO_WRITE_DEPTH=16, PROG_EMPTY_THRESH=5
Figure 7. Standard Write Operation with Empty Deassertion. FIFO_WRITE_DEPTH=16
Figure 8. Standard Read Operation with Full Deassertion. FIFO_WRITE_DEPTH=16, FIFO_READ_LATENCY=1
Port Descriptions
| Port | Direction | Width | Domain | Sense | Handling if Unused | Function |
|---|---|---|---|---|---|---|
| almost_empty | Output | 1 | wr_clk | LEVEL_HIGH | DoNotCare | Almost Empty : When asserted, this signal indicates that only one more read can be performed before the FIFO goes to empty. |
| almost_full | Output | 1 | wr_clk | LEVEL_HIGH | DoNotCare | Almost Full: When asserted, this signal indicates that only one more write can be performed before the FIFO is full. |
| data_valid | Output | 1 | wr_clk | LEVEL_HIGH | DoNotCare | Read Data Valid: When asserted, this signal indicates that valid data is available on the output bus (dout). |
| dbiterr | Output | 1 | wr_clk | LEVEL_HIGH | DoNotCare | Double Bit Error: Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted. |
| din | Input | WRITE_DATA_WIDTH | wr_clk | NA | Active | Write Data: The input data bus used when writing the FIFO. |
| dout | Output | READ_DATA_WIDTH | wr_clk | NA | Active | Read Data: The output data bus is driven when reading the FIFO. |
| empty | Output | 1 | wr_clk | LEVEL_HIGH | Active |
Empty Flag: When asserted, this signal indicates that the FIFO is empty. Read requests are ignored when the FIFO is empty, initiating a read while empty is not destructive to the FIFO. |
| full | Output | 1 | wr_clk | LEVEL_HIGH | Active |
Full Flag: When asserted, this signal indicates that the FIFO is full. Write requests are ignored when the FIFO is full, initiating a write when the FIFO is full is not destructive to the contents of the FIFO. |
| injectdbiterr | Input | 1 | wr_clk | LEVEL_HIGH | 0 | Double Bit Error Injection: Injects a double bit error if the ECC feature is used on block RAMs or UltraRAM macros. |
| injectsbiterr | Input | 1 | wr_clk | LEVEL_HIGH | 0 | Single Bit Error Injection: Injects a single bit error if the ECC feature is used on block RAMs or UltraRAM macros. |
| overflow | Output | 1 | wr_clk | LEVEL_HIGH | DoNotCare | Overflow: This signal indicates that a write request (wren) during the prior clock cycle was rejected, because the FIFO is full. Overflowing the FIFO is not destructive to the contents of the FIFO. |
| prog_empty | Output | 1 | wr_clk | LEVEL_HIGH | DoNotCare |
Programmable Empty: This signal is asserted when the number of words in the FIFO is less than or equal to the programmable empty threshold value. It is de-asserted when the number of words in the FIFO exceeds the programmable empty threshold value. |
| prog_full | Output | 1 | wr_clk | LEVEL_HIGH | DoNotCare |
Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal to the programmable full threshold value. It is de-asserted when the number of words in the FIFO is less than the programmable full threshold value. |
| rd_data_count | Output | RD_DATA_COUNT_WIDTH | wr_clk | NA | DoNotCare | Read Data Count: This bus indicates the number of words read from the FIFO. |
| rd_en | Input | 1 | wr_clk | LEVEL_HIGH | Active | Read Enable: If the FIFO is not empty, asserting this signal causes data (on dout) to be read from the FIFO.
|
| rd_rst_busy | Output | 1 | wr_clk | LEVEL_HIGH | DoNotCare | Read Reset Busy: Active-High indicator that the FIFO read domain is currently in a reset state. |
| rst | Input | 1 | wr_clk | LEVEL_HIGH | Active | Reset: Must be synchronous to wr_clk. The clock(s) can be unstable at the time of applying reset, but reset must be released only after the clock(s) is/are stable. |
| sbiterr | Output | 1 | wr_clk | LEVEL_HIGH | DoNotCare | Single Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error. |
| sleep | Input | 1 | NA | LEVEL_HIGH | 0 | Dynamic power saving- If sleep is High, the memory/fifo block is in power saving mode. |
| underflow | Output | 1 | wr_clk | LEVEL_HIGH | DoNotCare | Underflow: Indicates that the read request (rd_en) during the previous clock cycle was rejected because the FIFO is empty. Under flowing the FIFO is not destructive to the FIFO. |
| wr_ack | Output | 1 | wr_clk | LEVEL_HIGH | DoNotCare | Write Acknowledge: This signal indicates that a write request (wr_en) during the prior clock cycle is succeeded. |
| wr_clk | Input | 1 | NA | EDGE_RISING | Active | Write clock: Used for write operation. wr_clk must be a free running clock. |
| wr_data_count | Output | WR_DATA_COUNT_WIDTH | wr_clk | NA | DoNotCare | Write Data Count: This bus indicates the number of words written into the FIFO. |
| wr_en | Input | 1 | wr_clk | LEVEL_HIGH | Active | Write Enable: If the FIFO is not full, asserting this signal causes data (on din) to be written to the FIFO
|
| wr_rst_busy | Output | 1 | wr_clk | LEVEL_HIGH | DoNotCare | Write Reset Busy: Active-High indicator that the FIFO write domain is currently in a reset state. |
Design Entry Method
| Instantiation | Yes |
| Inference | No |
| IP and IP Integrator Catalog | No |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| CASCADE_HEIGHT | DECIMAL | 0 to 64 | 0 |
0- No Cascade Height, Allow Vivado Synthesis to choose. 1 or more - Vivado Synthesis sets the specified value as Cascade Height. |
| DOUT_RESET_VALUE | STRING | String | "0" | Reset value of read data path. |
| ECC_MODE | STRING | "no_ecc", "en_ecc" | "no_ecc" |
|
| EN_SIM_ASSERT_ERR | STRING | String | "warning" |
|
| FIFO_MEMORY_TYPE | STRING | "auto", "block", "distributed", "ultra" | "auto" | Designate the fifo memory primitive (resource type) to use-
|
| FIFO_READ_LATENCY | DECIMAL | 0 to 100 | 1 | Number of output register stages in the read data path
|
| FIFO_WRITE_DEPTH | DECIMAL | 16 to 4194304 | 2048 | Defines the FIFO Write Depth, must be power of two
|
| FULL_RESET_VALUE | DECIMAL | 0 to 1 | 0 | Sets full, almost_full and prog_full to FULL_RESET_VALUE during reset |
| PROG_EMPTY_THRESH | DECIMAL | 3 to 4194304 | 10 |
Specifies the minimum number of read words in the FIFO at or below which prog_empty is asserted.
If READ_MODE = "std", then READ_MODE_VAL = 0; Otherwise READ_MODE_VAL = 1. NOTE: The default threshold value is dependent on default FIFO_WRITE_DEPTH value. If FIFO_WRITE_DEPTH value is changed, ensure the threshold value is within the valid range though the programmable flags are not used. |
| PROG_FULL_THRESH | DECIMAL | 3 to 4194301 | 10 |
Specifies the maximum number of write words in the FIFO at or above which prog_full is asserted.
If READ_MODE = "std", then READ_MODE_VAL = 0; Otherwise READ_MODE_VAL = 1. NOTE: The default threshold value is dependent on default FIFO_WRITE_DEPTH value. If FIFO_WRITE_DEPTH value is changed, ensure the threshold value is within the valid range though the programmable flags are not used. |
| RD_DATA_COUNT_WIDTH | DECIMAL | 1 to 23 | 1 | Specifies the width of rd_data_count. To reflect the correct value, the width should be log2(FIFO_READ_DEPTH)+1.
|
| READ_DATA_WIDTH | DECIMAL | 1 to 4096 | 32 | Defines the width of the read data port, dout
|
| READ_MODE | STRING | "std", "fwft" | "std" |
|
| SIM_ASSERT_CHK | DECIMAL | 0 to 1 | 0 |
0- Disable simulation message reporting. Messages related to potential misuse will not be reported. 1- Enable simulation message reporting. Messages related to potential misuse will be reported. |
| USE_ADV_FEATURES | STRING | String | "0707" |
Enables data_valid, almost_empty, rd_data_count, prog_empty, underflow, wr_ack, almost_full, wr_data_count, prog_full, overflow features.
|
| WAKEUP_TIME | DECIMAL | 0 to 2 | 0 |
|
| WR_DATA_COUNT_WIDTH | DECIMAL | 1 to 23 | 1 | Specifies the width of wr_data_count. To reflect the correct value, the width should be log2(FIFO_WRITE_DEPTH)+1. |
| WRITE_DATA_WIDTH | DECIMAL | 1 to 4096 | 32 | Defines the width of the write data port, din
|