Versal CIPS and NoC (DDR) IP Core Configuration - 2023.2 English

Versal Adaptive SoC Embedded Design Tutorial (UG1305)

Document ID
UG1305
Release Date
2023-12-12
Version
2023.2 English

The AMD Versal™ Control, Interfaces and Processing System (CIPS) IP core allows you to configure the processing system and the PMC block, including boot mode, peripherals, clocks, interfaces, and interrupts, among other things.

This chapter describes how to perform the following tasks:

  • Creating an AMD Vivado™ project for Versal devices to select the appropriate boot devices and peripherals by configuring the CIPS IP core.

  • Creating and running a Hello World software application on the on-chip-memory (OCM) of the Arm® Cortex™-A72 processor.

  • Creating and running a Hello World software application on the tightly-coupled-memory (TCM) of the Arm Cortex-R5F processor.

The NoC IP core configures the DDR memory and data path across the DDR memory and processing engines in the system (Scalar Engines, Adaptable Engines, and AI Engines).

  • Creating and running a Hello World software application on Arm Cortex-A72 using DDR as memory.

  • Creating and running a Hello World software application on Arm Cortex-R5F using DDR as memory.

Note

The design files for this chapter have been validated with Vivado Design Suite 2022.1.

Prerequisites

To create and run Hello World applications discussed in this chapter, install the AMD Vitis™ unified software platform. For installation procedures, see Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400).

CIPS IP Core Configuration

Creating a Versal system design involves configuring the CIPS IP core to select the appropriate boot devices and peripherals. To start with, if the CIPS IP core peripherals and available multiplexed I/O (MIO) connections meet the requirements, no PL component is required. This chapter guides you through creating a simple CIPS IP core-based design.

Creating a New Embedded Project with a Versal Device

For this example, launch the Vivado Design Suite and create a project with an embedded processor system as the top level.

Starting Your Design

  1. Start the Vivado Design Suite.

  2. Optional: This step is required only if you have an ES1 board. In the Tcl Console, type the following command to enable ES1 boards:

    enable_beta_device
    

    Press Enter.

    Note

    You have to add enable_beta_device in the ~/.Xilinx/Vivado/Vivado_init.tcl (Linux host) too.

  3. In the Vivado Quick Start page, click Create Project to open the New Project wizard.

  4. Use the following information in the table to make selections in each of the wizard screens.

    Table 1: System Property Settings

    Wizard Screen System

    System Property

    Setting or Command to Use

    Project Name

    Project Name

    edt_versal

    Project Location

    C:/edt

    Create Project Subdirectory

    Leave this checked

    Project Type

    Specify the type of project to create. You can start with RTL or a synthesized EDIF

    RTL Project

    Do not specify sources at this time check box

    Leave this unchecked

    Project is an extensible Vitis platform checkbox

    Leave this unchecked

    Add Sources

    Do not make any changes to this screen

    Add Con straints

    Do not make any changes to this screen

    Default Part

    Select

    Boards

    Display Name

    Versal VMK180/VCK190/VPK180 Evaluation Platform

    Project Summary

    Project Summary

    Review the project summary

    Note

    Select Display Name as VPK180 Evaluation platform for creating project for SSI devices.

  5. Click Finish. The New Project wizard closes and the project you just created opens in the Vivado design tool.

    Note

    Check the version number while choosing a board. For ES1 silicon, the board version is 1.3. For production silicon, the board version is 2.2. Select the version based on the silicon on the board.

Creating an Embedded Processor Project

To create an embedded processor project:

  1. In the Flow Navigator, under IP integrator, click Create Block Design.

    ../_images/image5.png

    The Create Block Design wizard opens.

  2. Use the following information to make selections in the Create Block Design wizard.

    Wizard Screen

    System Property

    Setting or Command to Use

    Create Block Design

    Design Name

    edt_versal

    Directory

    <Local to Project>

    Specify Source Set

    Design Sources

  3. Click OK.

    The diagram window view opens with a message that states that this design is empty. To get started, add an IP from the IP catalog.

  4. Click the Add IP button add_ip.

  5. In the search box, type CIPS to find the Control, Interfaces and Processing System.

  6. Double-click the Control, Interface & Processing System IP to add it to the block design. The CIPS IP core appears in the diagram view, as shown in the following figure:

    ../_images/image7.png

Managing the Versal CIPS IP Core in the Vivado Design Suite

Now that you have added the processor system for Versal devices to the design, you can begin managing the available options.

  1. Click Run Block Automation.

  2. Configure the run block settings as shown in the following figure:

    ../_images/run-automation-1.png
  3. Double-click versal_cips_0 in the Block Diagram window.

  4. Ensure that all the settings for Design Flow and Presets are as shown in the following figure.

    ../_images/4-full-system.png
  5. Click Next, then click PS PMC.

    ../_images/ps-pmc.png

    Note

    VCK190 preset values will set QSPI and SD as the default boot modes. No changes are required.

  6. Click Interrupts and configure settings as shown in figure below:

    ../_images/interrupts.png
  7. Click OK and Finish to close the CIPS GUI.

Validating the Design and Generating the Output

To validate the design and to generate the output products, follow these steps:

  1. Right-click in the white space of the Block Diagram view and select Validate Design. Alternatively, you can press the F6 key. A message dialog box opens as shown below.

    Once the validation is complete, A message dialog box opens as shown below:

    ../_images/validation_message.PNG
  2. In the Block Design view, click Sources tab

  3. Click Hierarchy and Expand Design Sources Folder, right-click edt_versal and select Create HDL Wrapper.

    The Create HDL Wrapper dialog box opens. Use this dialog box to create an HDL wrapper file for the processor subsystem.

    Tip

    The HDL wrapper is a top-level entity required by the design tools.

  4. Select Let Vivado manage wrapper and auto-update and click OK.

  5. In the Block Design Sources window, under Design Sources, expand edt_versal_wrapper.

  6. Right-click the top-level block diagram, titled edt_versal_i: edt_versal (edt_versal.bd) and select Generate Output Products.

    The Generate Output Products dialog box opens, as shown in the following figure.

    ../_images/Generate_op_products_dial_box.png

    Note

    If you are running the Vivado Design Suite on a Windows machine, you might see different options under Run Settings. In this case, continue with the default settings.

  7. Click Generate.

    This step builds all the required output products for the selected source. You do not need to manually create constraints for the IP processor system. The Vivado Design Suite automatically generates the XDC file for the processor subsystem when you select Generate Output Products.

  8. In the Block Design Sources window, click the IP Sources tab. Here you can see the output products that you just generated, as shown in the following figure.

    ../_images/ip-sources.png

Synthesizing, Implementing, and Generating the Device Image

Follow these steps to generate a device image for the design.

  1. Go to Flow Navigator→ Program and Debug and click Generate Device Image.

  2. A No Implementation Results Available menu appears. Click Yes.

  3. A Launch Run menu appears. Click OK.

    When the Device Image Generation completes, the Device Image Generation Completed dialog box opens.

  4. Click Cancel to close the window.

  5. Export hardware after you generate the Device Image.

Note

The following steps are optional and you can skip these and go to the Exporting Hardware section. These steps provide the detailed flow for generating the device image by running synthesis and implementation before generating the device image. To understand the flow for generating the device image, follow these steps.

  1. Go to Flow Navigator→ Synthesis, click Run Synthesis and click OK.

    ../_images/image17.png
  2. If Vivado prompts you to save your project before launching synthesis, click Save.

    While synthesis is running, a status bar is displayed in the upper right-hand window. This status bar spools for various reasons throughout the design process. The status bar signifies that a process is working in the background. When synthesis is complete, the Synthesis Completed dialog box opens.

  3. Select Run Implementation and click OK.

    When implementation completes, the Implementation Completed dialog box opens.

  4. Select Generate Device Image and click OK.

    The Device Image Generation Completed dialog box opens.

  5. Click Cancel to close the window.

    Export the hardware after you generate the device image.

Exporting Hardware

  1. From the Vivado toolbar, select File → Export→ Export Hardware.

    The Export Hardware dialog box opens.

  2. Choose Include device image and click Next.

  3. Provide a name for your exported file (or use the default provided) and choose the location. Click Next.

    A warning message appears if a Hardware Module has already been exported. Click Yes to overwrite the existing XSA file, if the overwrite message is displayed.

  4. Click Finish.

Running a Bare-Metal Hello World Application

In this example, you will learn how to manage the board settings, make cable connections, connect to the board through your system, and run a Hello World software application from Arm Cortex-A72 on On-chip-memory (OCM) and Arm Cortex- R5F on Tightly-coupled-memory (TCM) on the Vitis software platform.

The following steps demonstrate the procedure to make the required cable connections, connect the board through your system, and launch the Vitis software platform.

  1. Connect the power cable to the board.

  2. Connect a USB Micro cable between the Windows host machine and USB JTAG connector on the target board. This cable is used for USB to serial transfer.

    Note

    Ensure that the SW1 switch is set to JTAG boot mode as shown in the following figure.

    ../_images/image19.jpeg
  3. Power on the VMK180/VCK190 board using the power switch as shown in the following figure.

    ../_images/vck190_production_board.jpg

    Note

    If the Vitis software platform is already running, jump to step 6.

  4. Launch the Vitis software platform by selecting Tools → Launch Vitis IDE from Vivado and set the workspace path, which in this example is c:\edt\edt_vck190.

    Alternatively, you can open the Vitis software platform with a default workspace and later switch it to the correct workspace by selecting File → Switch Workspace and then selecting the workspace.

  5. Open a serial communication utility for the COM port assigned to your system. The Vitis software platform provides a serial terminal utility, which is used throughout the tutorial. Select Window → Show View → Xilinx → Vitis Serial Terminal to open it.

    ../_images/image21.jpeg
  6. Click the Connect to a serial port button in the Vitis terminal context to set the serial configuration and connect it.

  7. Verify the port details in the Windows device manager.

    UART-0 terminal corresponds to Com-Port with Interface-0. For this example, UART-0 terminal is set by default, so for the Com-Port, select the port with interface-0. The following figure shows the standard configuration for the Versal devices processing system.