Starting Your Design¶

1. Start the Vivado Design Suite.

2. In the Vivado Quick Start page, click Create Project to open the New Project wizard.

3. Use the following information in the table to make selections in each of the wizard screens.

   Table 1: System Property Settings

   Wizard Screen System	System Property	Setting or Command to Use
   Project Name	Project Name	edt_versal
   	Project Location	C:/edt
   	Create Project Subdirectory	Leave this checked
   Project Type	Specify the type of project to create. You can start with RTL or a synthesized EDIF	RTL Project
   	Do not specify sources at this time check box	Leave this unchecked
   	Project is an extensible Vitis platform checkbox	Leave this unchecked
   Add Sources	Do not make any changes to this screen
   Add Con straints	Do not make any changes to this screen
   Default Part	Select	Boards
   	Display Name	Versal VMK180/VCK190/VPK180 Evaluation Platform
   Project Summary	Project Summary	Review the project summary

   Note

   Select Display Name as VPK180 Evaluation platform for creating project for SSI devices.

4. Click Finish. The New Project wizard closes and the project you just created opens in the Vivado design tool.

   Note

   Select the version based on the silicon on the board.For production silicon, select the board revision as Rev A01 with board file version as 1.2.

Creating an Embedded Processor Project¶

To create an embedded processor project:

1. In the Flow Navigator, under IP integrator, click Create Block Design.

   

   The Create Block Design wizard opens.

2. Use the following information to make selections in the Create Block Design wizard.

   Wizard Screen	System Property	Setting or Command to Use
   Create Block Design	Design Name	edt_versal
   	Directory	<Local to Project>
   	Specify Source Set	Design Sources

3. Click OK.

   The diagram window view opens with a message that states that this design is empty. To get started, add an IP from the IP catalog.

4. Click the Add IP button .

5. In the search box, type CIPS to find the Control, Interfaces and Processing System.

6. Double-click the Control, Interface & Processing System IP to add it to the block design. The CIPS IP core appears in the diagram view, as shown in the following figure:

   

Managing the Versal CIPS IP Core in the Vivado Design Suite¶

Now that you have added the processor system for Versal devices to the design, you can begin managing the available options.

1. Click Run Block Automation.

2. Configure the run block settings as shown in the following figure:

   

3. Double-click versal_cips_0 in the Block Diagram window.

4. Ensure that all the settings for Design Flow and Presets are as shown in the following figure.

   

5. Click Next, then click PS PMC.

   

   Note

   VCK190 preset values will set QSPI and SD as the default boot modes. No changes are required.

6. Click Interrupts and configure settings as shown in figure below:

   

7. Click OK and Finish to close the CIPS GUI.

Validating the Design and Generating the Output¶

To validate the design and to generate the output products, follow these steps:

1. Right-click in the white space of the Block Diagram view and select Validate Design. Alternatively, you can press the F6 key. A message dialog box opens as shown below.

   Once the validation is complete, A message dialog box opens as shown below:

   

2. In the Block Design view, click Sources tab

3. Click Hierarchy and Expand Design Sources Folder, right-click edt_versal and select Create HDL Wrapper.

   The Create HDL Wrapper dialog box opens. Use this dialog box to create an HDL wrapper file for the processor subsystem.

   Tip

   The HDL wrapper is a top-level entity required by the design tools.

4. Select Let Vivado manage wrapper and auto-update and click OK.

5. In the Block Design Sources window, under Design Sources, expand edt_versal_wrapper.

6. Right-click the top-level block diagram, titled edt_versal_i: edt_versal (edt_versal.bd) and select Generate Output Products.

   The Generate Output Products dialog box opens, as shown in the following figure.

   

   Note

   If you are running the Vivado Design Suite on a Windows machine, you might see different options under Run Settings. In this case, continue with the default settings.

7. Click Generate.

   This step builds all the required output products for the selected source. You do not need to manually create constraints for the IP processor system. The Vivado Design Suite automatically generates the XDC file for the processor subsystem when you select Generate Output Products.

8. In the Block Design Sources window, click the IP Sources tab. Here you can see the output products that you just generated, as shown in the following figure.

   

Synthesizing, Implementing, and Generating the Device Image¶

Follow these steps to generate a device image for the design.

1. Go to Flow Navigator→ Program and Debug and click Generate Device Image.

2. A No Implementation Results Available menu appears. Click Yes.

3. A Launch Run menu appears. Click OK.

   When the Device Image Generation completes, the Device Image Generation Completed dialog box opens.

4. Click Cancel to close the window.

5. Export hardware after you generate the Device Image.

Exporting Hardware¶

1. From the Vivado toolbar, select File → Export→ Export Hardware.

   The Export Hardware dialog box opens.

2. Choose Include device image and click Next.

3. Provide a name for your exported file (or use the default provided) and choose the location. Click Next.

   A warning message appears if a Hardware Module has already been exported. Click Yes to overwrite the existing XSA file, if the overwrite message is displayed.

4. Click Finish.

Creating a Hello World Application for the Arm Cortex-A72 on OCM¶

The following steps demonstrate the procedure to create a Hello World application from Arm Cortex-A72 on OCM.

Creating the Standalone Application Project for the Arm Cortex-R5F¶

The following steps demonstrate the procedure to create a Hello World application from Arm Cortex-R5F.

1. Select File > New Components > From Example.

2. Select Hello World and click Create Application Component from Template.

   

   Use the following information to make your selections on the wizard screens:

   Wizard Screen	System Properties	Setting or command to use
   Application Details	Component name	hello_world_r5
   	Component location	< Application path >
   	Hardware Design (XSA)	Select the platform created (Vck190_platform)
   Domain	Operating System	standalone
   	Processor	psv_cortexr5_0

3. Add the Component name and click Next.

4. Select the Created Platform and click Next.

5. Select Domain “standalone_psv_cortexr5_0” and click Next.

6. Click Finish and the Hello world Application is created successfully.

   

Creating a Run Configuration for the System Project¶

1. Select the component (hello_wolrd) application and Click On Run

2. Create a Run Configuration.

   

Creating a Run Configuration for a Single Application within a System Project¶

You can create a run configuration for a single application within a system project in two ways:

Configuring Your Design¶

To configure your design, follow these steps:

1. Open the design created in Creating a New Embedded Project with Versal Devices, edt_versal.xpr.

2. Open the block design, edt_versal.bd.

3. Add AXI NoC IP from the IP catalog.

4. Click Run Block Automation.

5. Make the run block settings as shown in the following figure:

   

6. Open CIPS → PS-PMC.

7. Click NoC. Enable the NoC Non-Coherent Interfaces PS to NoC Interface 0/1 as shown below.

   

8. Click OK and Finish to complete and exit CIPS configuration.

9. Double-click the NoC IP. From the General Tab, set Number of AXI Slave interfaces and AXI Clocks to 8:

   

10. From the Inputs tab, configure the following settings for S06 AXI and S07 AXI:

11. Configure the following settings from the Connectivity tab:

    

12. Click OK.

13. Make connections between CIPS and NoC as shown below

    

    This adds the AXI NoC IP for DDR access.

    

Validating the Design and Generating the Output¶

To validate the design and generate the output, follow these steps:

1. Right-click in the white space of the Block Diagram view and select Validate Design. Alternatively, you can press the F6 key. A message dialog box opens as shown below.

   The Vivado tool will prompt you to map the IPs in the design to an address. Click Yes.

   

   Note

   The number of address segments may vary depending on the number of memory mapped IPs in the design.

   Once the validation is complete, A message dialog box opens as shown below:

   

2. Click OK to close the message.

3. In the Block Design Sources window, under Design Sources, expand edt_versal_wrapper.

4. Right-click the top-level block diagram, titled edt_versal_i: edt_versal (edt_versal.bd) and select Generate Output Products.

   The Generate Output Products dialog box opens, as shown in the following figure.

   

   Note

   If you are running the Vivado Design Suite on a Windows machine, you might see different options under Run Settings. In this case, continue with the default settings.

5. Click Generate.

   This step builds all required output products for the selected source. You do not need to manually create constraints for the IP processor system. The Vivado Design Suite automatically generates the XDC file for the processor subsystem when you select Generate Output Products.

6. When the Generate Output Products process completes, click OK. Click the Design Runs window on the bottom window to see OOC Module Runs/Synthesis/Implementation runs.

7. In the Sources window, click the IP Sources view. Here you can see the output products that you just generated, as shown in the following figure.

   

Synthesizing, Implementing, and Generating the Device Image¶

Follow these steps to generate a device image for the design.

1. Go to Flow Navigator→ Program and Debug and click Generate Device Image.

2. A No Implementation Results Available menu appears. Click Yes.

3. A Launch Run menu appears. Click OK.

   When the Device Image Generation completes, the Device Image Generation Completed dialog box opens.

4. Click Cancel to close the window.

5. Export hardware after you generate the Device Image and click OK.

Exporting Hardware¶

1. From the Vivado main menu, select File→ Export → Export Hardware. The Export Hardware dialog box opens.

2. Choose Include device image and click Next.

3. Provide a name for your exported file (or use the default provided) and choose the location. Click Next.

   A warning message appears if a hardware module has already been exported. Click Yes to overwrite the existing XSA file, if the overwrite message is displayed.

4. Click Finish.