The AMD Versal™ Control, Interfaces and Processing System (CIPS) IP core allows you to configure the processing system and the PMC block, including boot mode, peripherals, clocks, interfaces, and interrupts, among other things.
This chapter describes how to perform the following tasks:
Creating an AMD Vivado™ project for Versal devices to select the appropriate boot devices and peripherals by configuring the CIPS IP core.
Creating and running a Hello World software application on the on-chip-memory (OCM) of the Arm® Cortex™-A72 processor.
Creating and running a Hello World software application on the tightly-coupled-memory (TCM) of the Arm Cortex-R5F processor.
The NoC IP core configures the DDR memory and data path across the DDR memory and processing engines in the system (Scalar Engines, Adaptable Engines, and AI Engines).
Creating and running a Hello World software application on Arm Cortex-A72 using DDR as memory.
Creating and running a Hello World software application on Arm Cortex-R5F using DDR as memory.
Note
The design files for this chapter have been validated with Vivado Design Suite 2022.1.