Versal Adaptive SoC Embedded Design Tutorial (UG1305) - 2023.2 English

Versal Adaptive SoC Embedded Design Tutorial (UG1305)

Document ID
UG1305
Release Date
2023-12-12
Version
2023.2 English

This document provides an introduction for using the AMD Vivado™ Design Suite flow for a VCK190/VMK180/VPK180 evaluation board. The tools used are Vivado Design Suite and the AMD Vitis™ unified software platform, version 2023.1. To install the Vitis unified software platform, see Vitis Unified Software Platform Documentation: Embedded Software Development [UG1400].

Note

In this tutorial, the instructions for booting Linux on the hardware is specific to the PetaLinux tools released for 2023.1, which must be installed on a Linux host machine for exercising the Linux portions of this document.

Important

The VCK190/VMK180 Evaluation kit has a Silicon Labs CP210x VCP USB-UART Bridge. Ensure that these drivers are installed. See the Silicon Labs CP210x USB-to-UART Installation Guide (UG1033) for more information.

The examples in this document are created using the AMD tools running on a Windows 10, 64-bit operating system, Vitis software platform and PetaLinux on a Linux 64-bit operating system. Other versions of the tools running on other Windows installs might provide varied results. These examples focus on introducing you to the following aspects of embedded design.

  • Versal CIPS and NoC (DDR) IP Core Configuration: Describes creation of a design with AMD Versal™ Adaptive SoC Control, Interfaces, and Processing System (CIPS) IP core and an NoC and running a simple “Hello World” application on Arm® Cortex™-A72, and Cortex-R5F processors. This chapter is an introduction to the hardware and software tools using a simple design as the example.

  • Boot and Configuration: Shows integration of components to configure and create boot images for Versal devices. The purpose of this chapter is to understand how to integrate and load boot loaders.

  • Debugging Using the Vitis Software Platform: Introduces debugging features of the Vitis software platform. This chapter uses the previous design and runs the software on bare metal (without an OS) to show the debugging features of the Vitis IDE. This chapter also lists debug configurations for Versal devices.

  • System Design Example using Scalar Engine and Adaptable Engine: Describes building a system on a Versal device using available tools and supported software blocks. This chapter demonstrates how to use the Vivado tool to create an embedded design using PL AXI GPIO. It also demonstrates the steps to configure and build the Linux operating system for an Arm Cortex-A72 core-based APU on a Versal device.

  • System Design Example for High-Speed Debug Port with SmartLynq+ Module: Describes building a system on a Versal device that utilizes the High-Speed Debug Port (HSDP). This chapter demonstrates how to use the Vivado tool to create an embedded design that utilizes HSDP and uses the SmartLynq+ module for downloading Linux images.

  • System Design Example for Versal Stacked Silicon Interconnect Devices: Describes building a system based on Versal devices using available tools and supported software blocks for Stacked Silicon Interconnect (SSI) devices.

This design tutorial requires use of a number of files provided by AMD. These are contained in a ZIP file that can be downloaded from the web site. (See Getting Started). The tutorial assumes the contents of the ZIP file are extracted to C:\edt.