Validating the Design and Generating the Output - Validating the Design and Generating the Output - 2025.2 English - UG1305

To validate the design and to generate the output product, follow these steps:

1. Return to the block design view and save your block design (press Ctrl+S).

2. Right-click in the white space of the Block Diagram view and select Validate Design. Alternatively, you can press the F6 key. A message dialog box opens as shown below.

   The Vivado tool prompts you to map the IPs in the design to an address. Click Yes.

   

   Note

   The number of address segments may vary depending on the number of memory mapped IPs in the design.

   Once the validation is complete, a message dialog box opens as shown below:

   

3. Click OK to close the message.

4. Click the Sources window.

   1. Expand Constraints.

   2. Right-click on constrs_1-> ADD Sources.

      The Add Sources window opens.

   3. Choose Add or Create Constraints option and click Next.

   4. Choose the .xdc file to be added.

      Note

      The constraints file is provided as part of the package in the pl_gpio_uart/constrs folder.

   5. Click Finish.

5. In the Block Design view, click Sources tab

6. Click Hierarchy and Expand Design Sources Folder, right-click edt_versal and select Create HDL Wrapper.

   The Create HDL Wrapper dialog box opens. Use this dialog box to create an HDL wrapper file for the processor subsystem.

   Tip

   The HDL wrapper is a top-level entity required by the design tools.

7. Select Let Vivado manage wrapper and auto-update and click OK.

8. In the Sources window, under Design Sources, expand edt_versal_wrapper.

9. Right-click the top-level block design, edt_versal_i : edt_versal (edt_versal.bd), and select Generate Output Products.

   

10. Click Generate.

11. When the Generate Output Products process completes, click OK.

12. In the Sources window, click the IP Sources view. Here, you can see the output products that you just generated, as shown in the following figure.