For more information on using PL hardware debug cores such as the AXIS-ILA, AXIS-VIO, PCIe™ Debugger, and/or DDRMC Calibration Interfaces refer to the Vivado Design Suite User Guide Programming and Debugging [UG908].
For more information on the SmartLynq+ Module, refer to `SmartLynq+ Module User Guide <https://www.xilinx.com/products/boards-and-kits/smartlynq-plus.html >`__.