System Design Example using Scalar Engine and Adaptable Engine - 2023.2 English

Versal Adaptive SoC Embedded Design Tutorial (UG1305)

Document ID
UG1305
Release Date
2023-12-12
Version
2023.2 English

This chapter guides you through building a system based on Versal™ devices using available tools and supported software blocks. This chapter demonstrates how to use the AMD Vivado™ Design Suite to create an embedded design using PL AXI GPIO and PL AXI UART. It also describes how to configure and build the Linux operating system for an Arm® Cortex™-A72 core-based APU on a Versal device.

Examples using the PetaLinux tool are provided in this chapter.

Note

The design files for this chapter have been validated with Vivado Design Suite 2022.1.

Design Example: Using AXI GPIO

The Linux application uses a PL-based AXI GPIO interface to monitor the DIP switch of the board and accordingly control the LEDs on the board. The LED application can run on VCK190 and VMK180 boards.

The RPU application uses the PL-based AXI UART lite to print the debug messages on the AXI UART console instead of using the PS UART console. The PL UART application can run on VCK190 and VMK180 boards.

Configuring Hardware

The first step in this design is to configure the PS and PL sections. You can do this using the Vivado IP integrator. Start with adding the required IPs from the Vivado IP catalog and then connect the components to blocks in the PS subsystem. To configure the hardware, follow these steps:

Note

If the Vivado Design Suite is open already, jump to step 3.

  1. Open the Vivado project you created in Versal CIPS and NoC (DDR) IP Core Configuration.

    C:/edt/edt_versal/edt_versal.xpr

  2. In the Flow Navigator, under IP Integrator, click Open Block Design.

    ../_images/image5.png
  3. Right-click the block diagram and select Add IP.

Connecting IP Blocks to Create a Complete System

To connect IP blocks to create a system, follow these steps.

  1. Double-click the Versal CIPS IP core.

  2. Click PS-PMC→ PS-PL Interfaces.

  3. Enable the M_AXI_FPD interface and set the Number of PL Resets to 1, as shown in the Image.

    ../_images/PS_PL_Interfaces.png
  4. Click Clocking, and then click on the Output Clocks tab.

  5. Expand PMC Domain Clocks. Then expand PL Fabric Clocks. Configure the PL0_REF_CLK to 300 MHz as shown in the following figure:

    ../_images/clocking_ps_PMC.png
  6. Click OK and Finish to complete the configuration and return to the block diagram.

Adding and Configuring IP Addresses

To add and configure IP addresses, follow these steps.

  1. Right-click the block diagram and select Add IP from the IP catalog.

  2. Search for AXI GPIO and double-click the AXI GPIO IP to add it to your design.

  3. Add another instance of the AXI GPIO IP into the design.

  4. Search for AXI Uartlite in the IP catalog and add it into the design.

  5. Click Run Connection Automation in the Block Design view.

    ../_images/image62.png

    The Run Connection Automation dialog box opens.

  6. In the Run Connection Automation dialog box, select the All Automation check box.

    ../_images/image63.png

    This checks the automation for all the ports of the AXI GPIO IP.

  7. Click GPIO of axi_gpio_0 and set the Select Board Part Interface to Custom as shown below.

    ../_images/image64.jpg
  8. Click S_AXI of axi_gpio_0. Set the configurations as shown in the following figure:

    ../_images/gpio_config0.png
  9. Repeat previous step 7 and Step 8 for axi_gpio_1.

  10. Click S_AXI of axi_uartlite_0. Set the configurations as shown in the following figure:

    ../_images/s-axi-uartlite.png
  11. This configuration sets the following connections:

    • Connects the S_AXI of AXI_GPIO and AXI Uartlite to M_AXI_FPD of CIPS with SmartConnect as a bridge IP between CIPS and AXI GPIO IPs.

    • Enables the processor system reset IP.

    • Connects the pl0_ref_clk to the processor system reset, AXI GPIO, and the SmartConnect IP clocks.

    • Connects the reset of the SmartConnect and AXI GPIO to the peripheral_aresetn of the processor system reset IP.

  12. Click UART of axi_uartlite_0. Set the configurations as shown in the following figure:

    ../_images/uart.png
  13. Click OK.

  14. Click Run Connection Automation in the block design window and select the All Automation check box.

  15. Click ext_reset_in and configure the setting as shown below.

    ../_images/image66.jpg

    This connects the ext_reset_in of the processor system reset IP to the pl_resetn of the CIPS.

  16. Click OK.

  17. Disconnect the aresetn of SmartConnect IP from peripheral_aresetn of processor system reset IP.

  18. Connect the aresetn of SmartConnect IP to interconnect_aresetn of processor system reset IP.

    ../_images/image67.jpeg
  19. Double-click the axi_gpio_0 IP to open it.

  20. Go to the IP Configuration tab and configure the settings as shown in the following figure.

    ../_images/image68.png
  21. Make the same setting for axi_gpio_1.

  22. Add four more instances of Slice IP.

  23. Delete the external pins of the AXI GPIO IP and expand the interfaces.

  24. Connect the output pin gpio_io_0 of axi_gpio_0 to slice 0 and slice 1.

  25. Similarly, connect the output pin gpio_io_0 of axi_gpio_1 to slice 2 and slice 3.

  26. Make the output of Slice IP as External.

  27. Configure each Slice IP as shown below.

    ../_images/image69.png ../_images/image70.png ../_images/image71.png ../_images/image72.png
  28. Double-click axi_uartlite_0 to open the IP.

  29. In the Board tab, set Board interface as shown below:

    ../_images/board-interface.png
  30. Go to the IP Configuration tab and configure the settings as shown in the following figure.

    ../_images/configure-ip-settings.png
  31. Add Clock Wizard IP. Double-click to open the IP.

  32. Go to Clocking Features tab and set the configuration as shown below:

    ../_images/clocking-features.png
  33. Make sure the Source option in Input Clock Information is set to Global buffer.

  34. Go to Output clocks tab and configure as follows: