System Design Example for Versal Stacked Silicon Interconnect Devices - 2023.2 English

Versal Adaptive SoC Embedded Design Tutorial (UG1305)

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2023.2 English

This chapter guides you through building a system based on AMD Versal™ devices using available tools and supported software blocks for Stacked Silicon Interconnect (SSI) devices. It explains how to create an embedded design utilizing PL AXI GPIO and PL AXI UART using the Vivado™ tool for the Versal Premium VP1802 SSI device based VPK180 board. Refer to the Documentation Reference Guide (UG949) for information on designing with SSI devices. It also describes configuring and building the Linux operating system for an Arm® Cortex™-A72 core-based APU for a targeted Versal device.


The design files for this chapter have been validated with Vivado Design Suite 2023.1.

Design Example: Using AXI GPIO

The design example uses PL-based AXI GPIO interfaces to control the LEDs on the board using a Linux application (gpiotest). To utilize the four Super Logic Regions (SLR) available in the VP1802 SSI technology device, the PL AXI GPIO interface paths for LED0, LED1, LED2, and LED3 are routed via SLR-0, SLR-1, SLR-2, and SLR-3, respectively.

The RPU bare-metal example application uses the PL-based AXI UART lite to print the debug messages on the AXI UART console instead of using the PS UART console.

The steps to configure the following are described in this design example:

  • Versal CIPS IP core configuration for SSI technology devices.

  • NoC (DDR) IP Core configuration and related connections required for SSI technology devices.

  • Configure AXI GPIO and AXI UART PL IPs and related connections to the CIPS via PS and PL interfaces.

Versal CIPS IP Core Configuration

The Versal CIPS IP core allows you to configure the processing system and the PMC block, including boot mode, peripherals, clocks, interfaces, and interrupts, among other things.

Managing the Versal CIPS IP Core in the Vivado Design Suite

  1. To create a new project and block design, follow the steps as given in Versal CIPS and NoC (DDR) IP Core Configuration.

  2. To get started, add an IP from the IP catalog by clicking the Add IP button.

  3. In the search box, type CIPS to find the Control, Interfaces, and Processing System.

  4. Double-click the Control, Interface & Processing System IP to add it to the block design. The CIPS IP core appears in the diagram view, as shown in the following figure:

  5. Click Run Block Automation.

  6. Configure the run block settings as shown in the following figure:

  7. Double-click versal_cips_0 in the Block Diagram window.

  8. Ensure that all the settings for Design Flow and Presets are as shown in the following figure.

  9. Click Next, then click PS PMC.

  10. Go to Peripherals and enable the TTC peripherals as shown in figure below:

  1. Make sure the IO configuration settings are as shown below:



VPK180 preset values will set QSPI and SD as the default boot modes. No changes are required.

  1. Click Interrupts and configure settings as shown in figure below:

  1. Click OK and Finish to close the CIPS GUI.

NoC (and DDR) IP Core Configuration

This section describes the NoC (and DDR) configuration and related connections required for use with the CIPS configured earlier in previous section. The NoC IP core allows configuring the NoC and enabling the DDR memory controllers.

Configuring NoC and CIPS

  1. Open CIPS → PS-PMC.

  2. Click NoC and enable the NoC coherent, non-coherent interfaces and the NoC to PMC interfaces for Master SLR (SLR-0) as shown below.

  3. Enable PMC to NoC and NoC to PMC connectivity for slave SLRs (SLR-1, SLR-2, SLR3) as shown below.

    ../_images/vpk_noc-interface-slr-1.png ../_images/vpk_noc-interface-slr-2.png ../_images/vpk_noc-interface-slr-3.png
  4. Click OK and Finish to close the CIPS GUI.

  5. Add two AXI NoC IP from the IP catalog.

  6. Double-click the axi_noc-0. From Board tab, enable the LPDDR triplet and associated clocks as shown below.