Modifying the Design to Enable the HSDP - Modifying the Design to Enable the HSDP - 2025.2 English - UG1305

This design uses the project built in System Design Example using Scalar Engine and Adaptable Engine and enables the HSDP interface. You can do this using the Vivado™ IP integrator.

1. Open the Vivado project you created in System Design Example using Scalar Engine and Adaptable Engine.

   C:/edt/edt_versal/edt_versal.xpr

2. In the Flow Navigator, under IP Integrator, click Open Block Design.

   

3. Double-click the Versal CIPS IP core to recustomize the IP. Click the Next button and click on the blue box labeled PS PMC to customize the Processing System (PS) and the Platform Management Controller (PMC). On the left pane, select Debug, then click on the HSDP tab.

   

4. Under High-Speed Debug Port (HSDP), select AURORA as the Pathway to/from Debug Packet Controller (DPC).

   

5. Set the following options: - GT Selection to HSDP1 GT - GT Refclk Selection to REFCLK1 - GT Refclk Freq (MHz) to 156.25

   Note

   Line rate is fixed at 10.0 Gb/s.

6. Click OK to save the changes. Two ports, gt_refclk1 and HSDP1_GT, are created on the CIPS IP.

7. On the IP Integrator page, right-click gt_refclk1 and select Make External. Do the same for HSDP1_GT.

   

8. Click Validate Design, then Save.