Managing the Versal CIPS IP Core in the Vivado Design Suite - Managing the Versal CIPS IP Core in the Vivado Design Suite - 2025.2 English - UG1305

1. To create a new project and block design, follow the steps as given in Versal CIPS and NoC (DDR) IP Core Configuration.

2. To get started, add an IP from the IP catalog by clicking the Add IP button.

3. In the search box, type CIPS to find the Control, Interfaces, and Processing System.

4. Double-click the Control, Interface and Processing System IP to add it to the block design. The CIPS IP core appears in the diagram view, as shown in the following figure:

   

5. Click Run Block Automation.

6. Configure the run block settings as shown in the following figure:

   

7. Double-click versal_cips_0 in the Block Diagram window.

8. Ensure that all the settings for Design Flow and Presets are as shown in the following figure.

   

9. Click Next, then click PS PMC.

   

   Note

   For non SSI technology devices, one PS PMC is available.

10. In PSPMC tab, go to Peripherals and enable the TTC peripherals as shown in figure below:

11. Make sure the IO configuration settings are as shown below:

Note

VPK180 preset values sets QSPI and SD as the default boot modes. No changes are required.

12. Click Interrupts and configure settings as shown in the figure below:

13. Click OK and Finish to close the CIPS GUI.