The design example uses PL-based AXI GPIO interfaces to control the LEDs on the board using a Linux application (gpiotest). To use the four Super Logic Regions (SLR) available in the VP1802 SSI technology device, the PL AXI GPIO interface paths for LED0, LED1, LED2, and LED3 are routed through SLR-0, SLR-1, SLR-2, and SLR-3, respectively.
The RPU bare-metal example application uses the PL-based AXI UART lite to print the debug messages on the AXI UART console instead of using the PS UART console.
The steps to configure the following are described in this design example:
Versal CIPS IP core configuration for SSI technology devices.
NoC (DDR) IP Core configuration and related connections required for SSI technology devices.
Configure AXI GPIO and AXI UART PL IPs and related connections to the CIPS through PS and PL interfaces.